SoC Encounter for Designers II - Integrated Systems Laboratory

5.1 Semester ProjectsThe MPW provider used for the semester projects offers modules caled Mini Asic (mini@sic) with asize of 1519.62 µm × 1519.62 µm. Therefore, the chip size for the semester project ASICs is fixed.Please refer to the following web page to learn the details.http://www.eda.ee.ethz.ch/index.php/UmcL180#Mini.40sicAs a consequence, we only have to make sure that our design fits on this area, and there is no needto find the smallest possible layout. We may however need to constrain the core area to make itsmaller if the utilization is too low, since a spread out design has longer interconnections that mayadversely affect timing.5.2 Sketching a FloorplanBefore we go on with CADENCE SOC ENCOUNTER we need to make some planning and understandsome key concepts. The figure on the following page is an example floorplan (not an ideal one) thatshows the important concepts.In CADENCE SOC ENCOUNTER die area corresponds to the total silicon area available to place pads(excluding bonding area for this technology) and core cells. For the semester projects this is strictlylimited to 1519.62 µm × 1519.62 µm. All pads (I/O, power and corner) are placed in what is knownas the padframe. The remaining area can be used for the core of the chip. For semester projectsthe theoretical maximum for core area is 1239.38 µm × 1239.38 µm = 1.54 mm 2 .As can be seen from the figure, the core area is surrounded by a core power ring. In its simplestform this consists of two (one for VCC, one for GND) wide 18 metal lines that evenly distribute the powerall around the chip. In order to leave room for the power ring, we need to leave a certain I/O to corespacing.The standard cells are designed in such a way that, when placed next to each other their VCC andGND pins can be connected with a horizontal power line. These horizontal lines are then extendedto the core power ring. These power connections are relatively narrow (0.76 µm in the technologythat we use) and run over the entire width of the core area. This could be a problem for designs thatconsume much power, since the cells towards the middle would not have a good power connection 19 .To improve this, vertical power stripes that connect to the horizontal power lines can be added,thereby forming sort of a mesh.The core area is filled with standard cell rows on which later all standard cells will be placed. In thesame area we will usually also need to make room for our macro-cells. Most macro-cells need somefree space around themselves. This free space is required to make signal connections, add a blockpower ring around the macro-cell or simply to prevent standard cells from being placed too close tothe macro-cell. We will define a block halo to specify this free space.18 The width of the metal line depends on the amount of current drawn from the line, you will be able to judge thisbetter after exercise 3 which is dedicated to estimating the power consumption. We will mostly use a width of 20 µm,since this is the widest metal that can be manufactured without slotting (wider metal lines require slots/holes whichbreak up the metal shape).19 The problem is that if much current is drawn, there will be a significant IR drop along the power lines. The cellsin the middle will be supplied with a lower VCC than the ones on the sides. This could dramatically effect theperformance of the system.16