SoC Encounter for Designers II - Integrated Systems Laboratory

We can see how the trees currently look like and what pins are connected to them. Look also at thetrace file directly. Things to look for include:• Clock, reset, or scan-enable connecting to unexpected input pins, e.g. the reset signal shouldnot connect to pins other than asynchronous set/reset pins of sequential elements.• Unexpected latches on the clock tree can be discovered this way (G or GB pin).• Discrepancy between the number of endpoints of clock, reset and scan trees. For our examplenumbers are as follows:– clock tree: 443 with 442 flip-flop CK pins + 1 RAM CK pin– reset tree: 441 flip-flop RB pins– scan tree: 447 with 441 flip-flop SEL pins + 6 mux S pins, to choose between the functionaland test (scan chain) output signal.As we see, 442 flip-flops are clocked but only 441 receive a reset signal, this is due to the resetsynchronization register being connected to the external reset signal rather than the internalreset tree. As the reset synchronization flip-flop is also not on the scan chain and we use fullscan otherwise the 441 flip-flops on the scan tree match perfectly. You get the idea...Student Task 29:• Open the file chip.cts trace and search for Clock Tree to examine the leaf pins.• If everything looks OK we can proceed with clock synthesis. In the SYNTHESIZE CLOCKTREE form press OK.After a few minutes clock tree synthesis will be completed. Detailed reports will be generated underthe directory specified on the form (most likely clock report). This directory includes a simple reportfile (clock.report).36