SoC Encounter for Designers II - Integrated Systems Laboratory

Student Task 31:• Copy your timing constraints file to filter_chip_postCTS.sdc and then modify the I/Otiming constraints to account for the insertion delay of the actual clock tree, make surethat the clock is set to PROPAGATED MODE and load the constraints (Timing →Load \Timing Constraint ... a )• Run timing analysis (make sure to select POST-CTS as design stage).• Examine the reports timingReports/chip postCTS * . You should now see the real timing onthe clock network.• If you have violations, run a POST-CTS (!) optimization with default settings. This shouldfix all violations.• Save the entire design.aCurrently loaded constraints will be purged before the new ones get loaded.10 Signal RoutingWe will now route the signal nets. What you have seen so far are only trial-route nets that are notDRC clean and can therefore not be manufactured.Student Task 32:• There are two routing engines in CADENCE SOC ENCOUNTER . WRoute is the older oneand NanoRoute is supposed to be the latest and greatest. Start NanoRoute by selectingRoute →NanoRoute →Route.... A large window will open. Enable the INSERT DIODESoption (you can leave the DIODE CELL NAME field blank) and leave all other settings at theirdefaults a . Click OK to start routing. You can observe the progress in the console window.aOn multi-CPU or multi-core machines you can increase the number of CPUs used by selecting Set MultipleCPU. This gives almost a linear speedup.The FIX ANTENNA and INSERT DIODE will cause the router to change layers and/or insert specialprotection diodes in order to avoid damages that can happen during manufacturing due to chargesthat accumulate on the wires and stress the gate oxide of input pins. Note that this is usually referredto as PROCESS ANTENNAS which is entirely different from geometrical antennas (which is related todangling wires).40