Aviation Electronics Technician 1 - Historic Naval Ships Association

Figure 1-5.-Manchester decoding.Because this makes both inputs to the second AND gateto be 1’s, the output of the second AND gate will be 1.This 1 will cause the integrator to charge, producing aManchester word bit of 1 during the second half of theclock pulse. This type of bit is generated for timingpurposes only.Manchester Word DecodingWhen component receives a Manchester word, thedigital control circuits must decode the word into thebasic binary word and the clock pulse train. This processis required prior to any further processing of the signalby the component. A Manchester decoder equivalentcircuit and its input and output signals are shown infigure 1-5.The first input bit of the Manchester is always a 1.This produces a 0 at the output of the inverter and theinputs of the two timers. The same Manchester input bitis applied to one input of the NAND gate. The 0 outputof the 8.3 timer is applied to the other input of the NANDgate, giving an output of 1 from the NAND gate. This 1is applied to the OR gate, making its output a 1. The 1from the OR gate represents the first derived clock pulsebit. This 1 is also applied to one of the inputs of the ANDgate. The other input is the original 1 from theManchester word. With both inputs to the AND gatebeing 1, the output will be a 1. This 1 represents the firstbit of the derived basic data bit.When the Manchester bit goes to 0, the inverteroutput goes to 1 and starts the two timers. If the nextManchester bit is 1, the two timers are restarted before1-7