F224d Faria, Rubens Alexandre de Desenvolvimento de ... - UTFPR

More documents

Recommendations

Info

AT-111I, pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. PSEN Program Store Enable is the read strobe to external program memory. When the AT89C52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EANpp External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to V cc for internal program executions. This pin also receives the 12-volt programming enable voltage (Vpp) during Flash programming when 12-volt programming is selected. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. Table 1. OF8H ( FFH OFOH B 00000000 F7H OE8H EFH OEOH ACC 00000000 E7H OD8H ODFH ODOH 0C8H OCOH PSW 00000000 T2CON 00000000 T2MOD XXXXXX00 RCAP2L 00000000 RCAP2H 00000000 TL2 00000000 TH2 00000000 OD7H OCFH 0C7H OB8H IP XX000000 OBFH OBOH P3 11111111 OB7H 0A8H I E OX000000 OAFH OAOH P2 11111111 0A7H 98 SCON 00000000 SBUF XXXXXXXX 9FH 90 88 80 i P1 11111111 TCON 00000000 PO 11111111 TMOD 00000000 SP 00000111 TLO 00000000 DPL 00000000 TL1 00000000 DPH 00000000 THO 00000000 TH1 00000000 PCON OXXX0000 97H 8FH 87H 4-64 AT89C52
AT89C52 Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indetermi- nate effect. User software should not write 1 s to these unlisted locations, since they may be used in future products to invoke Table 2. T2CON—Timer/Counter 2 Control Register new T2CON Address = 0C8H Bit Addressable features. In that case, the reset or inactive values of the new bits will always be 0. Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 4) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode. Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register. tinnQ n Hesei value = uvu,, ,,,,..., Bit TF2 EXF2 RCLK TCLK EXEN2 TR2 CTT2 CP/RL2 7 6 5 4 3 2 1 0 Symbol TF2 EXF2 RCLK TCLK EXEN2 Function Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1 or TCLK = 1. Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1). Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer. Cfr2 Timer or counter select for Timer 2. C a2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered). Capture/Reload select. CP/RL2 =1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 CP/R L2 = 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. Data Memory The AT89C52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location OAOH (which is P2). MOV OAOH, #data Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where RO contains OAOH, accesses the data byte at address OAOH, rather than P2 (whose address is OAOH). MOV @RO, #data Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space. Neff, 4-65
Page 1 and 2:
F224d Faria, Rubens Alexandre de De
Page 3 and 4:
7. COMPONENTE: TITULAcA0(siGLA): IN
Page 5 and 6:
CADASTRO DE PROFESSOR DE OUTRA INST
Page 7 and 8:
TESES / INFORMAQOES AREA DE CONHECI
Page 9 and 10:
RUBENS ALEXANDRE DE FARIA DESENVOLV
Page 11 and 12:
E finalmente o espaco reservado aos
Page 13 and 14:
2.12 INFLUENIA DE OUTROS FATORES Fi
Page 15 and 16:
ANEXO IV DIAGRAMAS ESQUEMATICOS 95
Page 17 and 18:
Figura 3 Desenho de uma incubadora
Page 19 and 20:
LISTA DE TABELAS Tabela 1 Temperatu
Page 21 and 22:
ABSTRACT In this work it is describ
Page 23 and 24:
2 em modificar as condicoes ambient
Page 25 and 26:
4 Neste capitulo foram apresentados
Page 27 and 28:
6 A incubadora dotada de controle a
Page 29 and 30:
8 penla de calor perda (le calor se
Page 31 and 32:
10 coeficiente varia de acordo corn
Page 33 and 34:
12 2.7.1 HIPERTERMIA A hipertermia
Page 35 and 36:
14 A medida adquirida no sensor de
Page 37 and 38:
16 incubadora para que a potencia s
Page 39 and 40:
18 parede do equipamento. Desse mod
Page 41 and 42:
20 Tabela 1 - Temperatura da incuba
Page 43 and 44:
22 de 80 dB (FANAROFF & KLAUS, 1995
Page 45 and 46:
CAPITULO 3 A CERTIFICAcAO DO EQUIPA
Page 47 and 48:
26 Segundo o INMETRO (Instituto Nac
Page 49 and 50:
28 10/03/1998. 0 OCP deve assegurar
Page 51 and 52:
30 A rede eletrica de 127 ou 220 V
Page 53 and 54:
32 0 modo de controle termico da in
Page 55 and 56:
34 sonoro. A indicacao visual deve
Page 57 and 58:
36 A norma NBR IEC 601-2-19 equipam
Page 59 and 60:
38 tipos de reuniao, confeccionando
Page 61 and 62:
40 ALTMENTACAO GERADOR RESET BARRAM
Page 63 and 64:
42 0 diagrama esquematico correspon
Page 65 and 66:
44 a escala atraves de potenciometr
Page 67 and 68:
46 Urn byte de controle e o primeir
Page 69 and 70:
48 0 maior problema dos sensores qu
Page 71 and 72:
50 A saida do sensor HC600 fornece
Page 73 and 74: 52 4.3.4.2 DISPLAY DE CRISTAL LIQUI
Page 75 and 76: 54 4.3.4.3 CONTROLE DE TEMPERATURA
Page 77 and 78: 56 CONSTMAIS: DB 00H,10H,F2H,DOH DB
Page 79 and 80: 58 (a) 4-+ 5mskliv 2V1div (b) 5ms/d
Page 81 and 82: 60 4.3.5 ALARMES E ATUADORES 4.3.5.
Page 83 and 84: 62 ar, pelo menos 3 minutos ap6s o
Page 85 and 86: 64 esta tarefa pois cada temperatur
Page 87 and 88: 66 0 tempo para aquecer a incubador
Page 89 and 90: 68 ma tambem esta entre os sensores
Page 91 and 92: 70 almente e seria especifico para
Page 93 and 94: CAPITULO 6 DISCUSSAO GERAL E CONCLU
Page 95 and 96: 74 Um problema que deve ser resolvi
Page 97 and 98: 76 ANEXO I LABORATORIOS CREDENCIADO
Page 99 and 100: 78 ANEXO II TOPICOS DA NORMA TECNIC
Page 101 and 102: 80 Temperatura de Controle: Tempera
Page 103 and 104: 82 IDENTIFICAcAO, MARCACAO E DOCUME
Page 105 and 106: 84 SEcA0 SETE - PROTE00 CONTRA TEMP
Page 107 and 108: 86 SEcA0 OITO - EXATIDAO NOS DADOS
Page 109 and 110: 88 tensao nominal e o equipamento o
Page 111 and 112: 90 - Onde urn movimento relativo de
Page 113 and 114: 92 - Na utilizacao normal, a veloci
Page 115 and 116: 94 CRONOGRAMA DE ATIVIDADES PARA 0
Page 117 and 118: W gEtq 1 w f 2 8 g .11 IF 2 0 CO MU
Page 119 and 120: ID —• 0) 1° 1• O C 03 LI N.)
Page 121 and 122: Features • Compatible with MCS-51
Page 123: AT89C52 The AT89C52 provides the fo
Page 127 and 128: 106 ANEXO VI CARACTERISTICAS TECNIC
Page 129 and 130: 108 tura é efetuada em 13 bits de
Page 131 and 132: 110 ANEXO VII CARACTERISTICAS TECNI
Page 133 and 134: 112 Tabela VII.II - Valores maximos
Page 135 and 136: 114 ANEXO VIII FOTOS DAS PLATAFORMA
Page 137 and 138: 116 Figura VIII.III - Hardware fina
Page 139 and 140: 118 Figura VIII.VII - Incubadora em
Page 141 and 142: 120 REFERENCIAS BIBLIOGRAFICAS 1. A
Page 143: 122 21. SEGRE, C. A. M. RN (Recem -
show all

F224d Faria, Rubens Alexandre de Desenvolvimento de ... - UTFPR

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?