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Table 3: Load modulation circuit.
Series Resistance 300 Ω
Current (max) 4 mA
ON Time < 10 ns
OFF Time < 10 ns
Leakage Current < 1 µA
Table 4: Schmitt trigger circuit.
Current Consumption
(static)
780 nA @ 1.9 V
ON Time 300 ± 50 µs
OFF Time 300 ± 50 µs
Threshold 0.9 V ± 0.1 V
Figure 11: Schmitt trigger circuit.
modulation signal is obtained from the digital part of
the front end. Transistor M1, in figure 10 acts as a
switch. The load resistor Rload works as a damping to
the antenna via the rectifier. This can be sensed by the
reader because of the coupling via the reader tag coils.
Table 3 contains some characteristic data regarding
the load modulation circuit. The currents may be quite
large (up to 4 mA) by direct coupling (small distances),
so the layout of the circuit must be accomplished
with adequate dimensions of resistor and routing.
B. Field detector circuit
The Schmitt trigger circuit is used to detect the field.
A low pass filter is used along with the Schmitt trigger
as shown in figure 3. The low pass filter is used to
suppress noise and short spikes, so that a minimum of
field energy must be available before the output is
going high. The circuit used here, as shown in figure
11, is a classical Schmitt trigger circuit, where the
threshold is controlled by W/L relations.
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REALIZATION OF AN RFID FRONT END IC FOR ISO 15693
STANDARD IN UMC CMOS 0.18 µM TECHNOLOGY
Figure 12: Block diagram showing the envelope detection for demodulator.
Figure 13: Comparator Circuit.
The threshold is adjusted in such a way that the output
only signals a field if there is enough energy to
supply the bandgap circuit and the demodulator. The
static current consumption is below 1 µA. Table 4
shows the characteristic data.
C. Demodulation
The circuit demodulates the ASK signal received
from the reader. The circuit comprises of an envelope
detector with a load capacitor, followed by a high pass
filter and a comparator. The rectifier shown in figure
12 and the load capacitance make the envelope detector.
The needed resistive load for the envelope detector
comes from the power consumption of the bandgap
circuit. The high pass filter strips the modulation from
the envelope and the comparator generates the digital
signal.
The comparator circuit used is a standard PMOS
single-stage comparator as shown in figure 13. The
comparator is supplied by the internal power supply of
1.2 V, available from the bandgap reference. The input
is referenced to ground, so the comparator must be
designed in such a way that ground is inside the allowed
input range. A hysteresis of 4 mV is provided to
suppress noise. An offset voltage of 25 mV is built