datasheet (3).pdf - EEWeb

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dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04 REGISTER 7-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 FLTA1IE RTCIE DMA5IE — — QEI1IE PWM1IE — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FLTA1IE: PWM1 Fault A Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 14 RTCIE: Real-Time Clock and Calendar Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13 DMA5IE: DMA Channel 5 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12-11 Unimplemented: Read as ‘0’ bit 10 QEI1IE: QEI1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 9 PWM1IE: PWM1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8-0 Unimplemented: Read as ‘0’ DS70291E-page 112 © 2011 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04 REGISTER 7-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 DAC1LIE (2) DAC1RIE (2) — — QEI2IE FLTA2IE PWM2IE — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — C1TXIE (1) DMA7IE DMA6IE CRCIE U2EIE U1EIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DAC1LIE: DAC Left Channel Interrupt Enable bit (2) 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 14 DAC1RIE: DAC Right Channel Interrupt Enable bit (2) 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13-12 Unimplemented: Read as ‘0’ bit 11 QEI2IE: QEI2 Event Interrupt Flag Status bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 10 FLTA2IE: PWM2 Fault A Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 9 PWM2IE: PWM2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8-7 Unimplemented: Read as ‘0’ bit 6 C1TXIE: ECAN1 Transmit Data Request Interrupt Enable bit (1) 1 = Interrupt request occurred 0 = Interrupt request not occurred bit 5 DMA7IE: DMA Channel 7 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4 DMA6IE: DMA Channel 6 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 CRCIE: CRC Generator Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 U2EIE: UART2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ Note 1: Interrupts are disabled on devices without ECAN modules. 2: Interrupts are disabled on devices without Audio DAC modules. © 2011 Microchip Technology Inc. DS70291E-page 113
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