datasheet (3).pdf - EEWeb

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dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04 FIGURE 31-22: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx SDAx IM31 IM34 IM30 IM33 Start Condition Note: Refer to Figure 31-1 for load conditions. Stop Condition FIGURE 31-23: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) SCLx SDAx In SDAx Out IM11 IM20 Note: Refer to Figure 31-1 for load conditions. IM11 IM10 IM26 IM10 IM25 IM33 IM40 IM40 IM45 DS70291E-page 380 © 2011 Microchip Technology Inc. IM21
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04 TABLE 31-40: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param No. Symbol Characteristic Min (1) Max Units Conditions IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — μs — 400 kHz mode TCY/2 (BRG + 1) — μs — 1 MHz mode (2) TCY/2 (BRG + 1) — μs — IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1) — μs — 400 kHz mode TCY/2 (BRG + 1) — μs — 1 MHz mode (2) TCY/2 (BRG + 1) — μs — IM20 TF:SCL SDAx and SCLx Fall Time IM21 TR:SCL SDAx and SCLx Rise Time IM25 TSU:DAT Data Input Setup Time IM26 THD:DAT Data Input Hold Time IM30 TSU:STA Start Condition Setup Time IM31 THD:STA Start Condition Hold Time 100 kHz mode — 300 ns CB is specified to be 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode (2) — 100 ns 100 kHz mode — 1000 ns CB is specified to be 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode (2) — 300 ns 100 kHz mode 250 — ns — 400 kHz mode 100 — ns 1 MHz mode (2) 40 — ns 100 kHz mode 0 — μs — 400 kHz mode 0 0.9 μs 1 MHz mode (2) 0.2 — μs 100 kHz mode TCY/2 (BRG + 1) — μs Only relevant for 400 kHz mode TCY/2 (BRG + 1) — μs 1 MHz mode (2) TCY/2 (BRG + 1) — μs Repeated Start condition 100 kHz mode TCY/2 (BRG + 1) — μs After this period the 400 kHz mode TCY/2 (BRG + 1) — μs 1 MHz mode (2) TCY/2 (BRG + 1) — μs first clock pulse is generated IM33 TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — μs — Setup Time 400 kHz mode TCY/2 (BRG + 1) — μs 1 MHz mode (2) TCY/2 (BRG + 1) — μs IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — ns — Hold Time 400 kHz mode TCY/2 (BRG + 1) — ns 1 MHz mode (2) TCY/2 (BRG + 1) — ns IM40 TAA:SCL Output Valid 100 kHz mode — 3500 ns — From Clock 400 kHz mode — 1000 ns — 1 MHz mode (2) — 400 ns — IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be 400 kHz mode 1 MHz mode 1.3 — μs free before a new transmission can start (2) 0.5 — μs IM50 CB Bus Capacitive Loading — 400 pF — IM51 TPGD Pulse Gobbler Delay 65 390 ns See Note 3 Note 1: BRG is the value of the I 2C Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit (I2C)” (DS70195) in the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site for the latest dsPIC33F/PIC24H Family Reference Manual sections. 2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). 3: Typical value for this parameter is 130 ns. © 2011 Microchip Technology Inc. DS70291E-page 381
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