datasheet (3).pdf - EEWeb

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dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04 4.6 Interfacing Program and Data Memory Spaces The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/ X04 and dsPIC33FJ128MCX02/X04 architecture uses a 24-bit-wide program space and a 16-bit-wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. Aside from normal execution, the dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04 architecture provides two methods by which program space can be accessed during operation: • Using table instructions to access individual bytes or words anywhere in the program space • Remapping a portion of the program space into the data space (Program Space Visibility) Table instructions allow an application to read or write to small areas of the program memory. This capability makes the method ideal for accessing data tables that need to be updated periodically. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look-ups from a large table of static data. The application can only access the least significant word of the program word. TABLE 4-42: PROGRAM SPACE ADDRESS CONSTRUCTION Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write) Program Space Visibility (Block Remap/Read) Access Space 4.6.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. For table operations, the 8-bit Table Page register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG = 0) or the configuration memory (TBLPAG = 1). For remapping operations, the 8-bit Program Space Visibility register (PSVPAG) is used to define a 16K word page in the program space. When the Most Significant bit of the EA is ‘1’, PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike table operations, this limits remapping operations strictly to the user memory area. Table 4-42 and Figure 4-9 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P refers to a program space word, and D refers to a data space word. Program Space Address User 0 PC 0 0xx xxxx xxxx xxxx xxxx xxx0 User TBLPAG Data EA 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG Data EA 1xxx xxxx xxxx xxxx xxxx xxxx User 0 PSVPAG Data EA (1) 0 xxxx xxxx xxx xxxx xxxx xxxx Note 1: Data EA is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG. DS70291E-page 72 © 2011 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04 FIGURE 4-9: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter (1) Table Operations (2) Program Space Visibility (1) (Remapping) 0 1/0 0 User/Configuration Space Select TBLPAG 8 bits Select PSVPAG 8 bits Program Counter 23 bits 24 bits © 2011 Microchip Technology Inc. DS70291E-page 73 1 23 bits EA 16 bits EA 15 bits 0 1/0 0 Byte Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word aligned. Table read operations are permitted in the configuration memory space.
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