datasheet (3).pdf - EEWeb

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dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04 15.1 Output Compare Modes Configure the Output Compare modes by setting the appropriate Output Compare Mode (OCM) bits in the Output Compare Control (OCxCON) register. Table 15-1 lists the different bit settings for the Output Compare modes. Figure 15-2 illustrates the output compare operation for various modes. The user application must disable the associated timer when writing to the output compare control registers to avoid malfunctions. FIGURE 15-2: OUTPUT COMPARE OPERATION Note 1: Only OC1 and OC2 can trigger a DMA data transfer. 2: See Section 13. “Output Compare” (DS70209) in the “dsPIC33F/PIC24H Family Reference Manual” for OCxR and OCxRS register restrictions. TABLE 15-1: OUTPUT COMPARE MODES OCM Mode OCx Pin Initial State OCx Interrupt Generation 000 Module Disabled Controlled by GPIO register — 001 Active-Low One-Shot 0 OCx Rising edge 010 Active-High One-Shot 1 OCx Falling edge 011 Toggle Mode Current output is maintained OCx Rising and Falling edge 100 Delayed One-Shot 0 OCx Falling edge 101 Continuous Pulse mode 0 OCx Falling edge 110 PWM mode without fault 0, if OCxR is zero No interrupt protection 1, if OCxR is non-zero 111 PWM mode with fault protection 0, if OCxR is zero 1, if OCxR is non-zero OCFA Falling edge for OC1 to OC4 TMRy Active Low One-Shot (OCM = 001) Active High One-Shot (OCM = 010) Toggle Mode (OCM = 011) Delayed One-Shot (OCM = 100) Continuous Pulse Mode (OCM = 101) PWM Mode (OCM = 110 or 111) Output Compare Mode enabled OCxRS OCxR Timer is reset on period match DS70291E-page 206 © 2011 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04 REGISTER 15-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER (x = 1, 2, 3 or 4) U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — OCSIDL — — — — — bit 15 bit 8 U-0 U-0 U-0 R-0 HC R/W-0 R/W-0 R/W-0 R/W-0 — — — OCFLT OCTSEL OCM bit 7 bit 0 Legend: HC = Cleared in Hardware HS = Set in Hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 OCSIDL: Stop Output Compare in Idle Mode Control bit 1 = Output Compare x halts in CPU Idle mode 0 = Output Compare x continues to operate in CPU Idle mode bit 12-5 Unimplemented: Read as ‘0’ bit 4 OCFLT: PWM Fault Condition Status bit 1 = PWM Fault condition has occurred (cleared in hardware only) 0 = No PWM Fault condition has occurred (This bit is only used when OCM = 111). bit 3 OCTSEL: Output Compare Timer Select bit 1 = Timer3 is the clock source for Compare x 0 = Timer2 is the clock source for Compare x bit 2-0 OCM: Output Compare Mode Select bits 111 = PWM mode on OCx, Fault pin enabled 110 = PWM mode on OCx, Fault pin disabled 101 = Initialize OCx pin low, generate continuous output pulses on OCx pin 100 = Initialize OCx pin low, generate single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled © 2011 Microchip Technology Inc. DS70291E-page 207
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