datasheet (3).pdf - EEWeb

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
Communication Modules:
• 4-wire SPI (up to two modules):
- Framing supports I/O interface to simple
codecs
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and
sampling modes
• I 2 C:
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
• UART (up to two modules):
- Interrupt on address bit detect
- Interrupt on UART error
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN 2.0 bus support
- IrDA ® encoding and decoding in hardware
- High-Speed Baud mode
- Hardware Flow Control with CTS and RTS
• Enhanced CAN (ECAN module) 2.0B active:
- Up to eight transmit and up to 32 receive buffers
- 16 receive filters and three masks
- Loopback, Listen Only and Listen All
- Messages modes for diagnostics and bus
monitoring
- Wake-up on CAN message
- Automatic processing of Remote
Transmission Requests
- FIFO mode using DMA
- DeviceNet addressing support
• Parallel Master Slave Port (PMP/EPSP):
- Supports 8-bit or 16-bit data
- Supports 16 address lines
• Programmable Cyclic Redundancy Check (CRC):
- Programmable bit length for the CRC
generator polynomial (up to 16-bit length)
- 8-deep, 16-bit or 16-deep, 8-bit FIFO for data
input
Packaging:
• 28-pin SDIP/SOIC/QFN-S
• 44-pin TQFP/QFN
Note: See Table 1 for the exact peripheral
features per device.
© 2011 Microchip Technology Inc. DS70291E-page 5