datasheet (3).pdf - EEWeb
datasheet (3).pdf - EEWeb
datasheet (3).pdf - EEWeb
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dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04<br />
Start and End Address................................................ 69<br />
W Address Register Selection .................................... 69<br />
Motor Control PWM .......................................................... 209<br />
Motor Control PWM Module<br />
2-Output Register Map................................................ 52<br />
6-Output Register Map................................................ 51<br />
MPLAB ASM30 Assembler, Linker, Librarian ................... 340<br />
MPLAB Integrated Development Environment Software .. 339<br />
MPLAB PM3 Device Programmer .................................... 342<br />
MPLAB REAL ICE In-Circuit Emulator System................. 341<br />
MPLINK Object Linker/MPLIB Object Librarian ................ 340<br />
N<br />
NVM Module<br />
Register Map............................................................... 66<br />
O<br />
Open-Drain Configuration ................................................. 164<br />
Output Compare ............................................................... 205<br />
P<br />
Packaging ......................................................................... 399<br />
Details ....................................................................... 400<br />
Marking ..................................................................... 399<br />
Peripheral Module Disable (PMD) .................................... 158<br />
Pinout I/O Descriptions (table) ............................................ 17<br />
PMD Module<br />
Register Map............................................................... 66<br />
PORTA<br />
Register Map......................................................... 64, 65<br />
PORTB<br />
Register Map............................................................... 65<br />
Power-on Reset (POR) ....................................................... 88<br />
Power-Saving Features .................................................... 157<br />
Clock Frequency and Switching................................ 157<br />
Program Address Space..................................................... 39<br />
Construction................................................................ 72<br />
Data Access from Program Memory Using Program<br />
Space Visibility.................................................... 75<br />
Data Access from Program Memory Using Table Instructions<br />
.................................................................... 74<br />
Data Access from, Address Generation...................... 73<br />
Memory Map ............................................................... 39<br />
Table Read Instructions<br />
TBLRDH ............................................................. 74<br />
TBLRDL .............................................................. 74<br />
Visibility Operation ...................................................... 75<br />
Program Memory<br />
Interrupt Vector ........................................................... 40<br />
Organization................................................................ 40<br />
Reset Vector ............................................................... 40<br />
Q<br />
Quadrature Encoder Interface (QEI)................................. 223<br />
Quadrature Encoder Interface (QEI) Module<br />
Register Map............................................................... 52<br />
R<br />
Reader Response ............................................................. 424<br />
Register Map<br />
CRC ............................................................................ 64<br />
Dual Comparator......................................................... 64<br />
Parallel Master/Slave Port .......................................... 63<br />
Real-Time Clock and Calendar................................... 64<br />
Registers<br />
AD1CHS0 (ADC1 Input Channel 0 Select ................ 284<br />
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select) ... 282<br />
AD1CON1 (ADC1 Control 1) .................................... 277<br />
AD1CON2 (ADC1 Control 2) .................................... 279<br />
AD1CON3 (ADC1 Control 3) .................................... 280<br />
AD1CON4 (ADC1 Control 4) .................................... 281<br />
AD1CSSL (ADC1 Input Scan Select Low) ............... 286<br />
AD1PCFGL (ADC1 Port Configuration Low) ............ 286<br />
CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer) .......... 259<br />
CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer) .......... 260<br />
CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer) ........ 260<br />
CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer) ...... 261<br />
CiCFG1 (ECAN Baud Rate Configuration 1)............ 257<br />
CiCFG2 (ECAN Baud Rate Configuration 2)............ 258<br />
CiCTRL1 (ECAN Control 1)...................................... 250<br />
CiCTRL2 (ECAN Control 2)...................................... 251<br />
CiEC (ECAN Transmit/Receive Error Count) ........... 257<br />
CiFCTRL (ECAN FIFO Control) ............................... 253<br />
CiFEN1 (ECAN Acceptance Filter Enable)............... 259<br />
CiFIFO (ECAN FIFO Status) .................................... 254<br />
CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection) .... 263,<br />
264<br />
CiINTE (ECAN Interrupt Enable) .............................. 256<br />
CiINTF (ECAN Interrupt Flag) .................................. 255<br />
CiRXFnEID (ECAN Acceptance Filter n Extended Identifier)<br />
................................................................... 263<br />
CiRXFnSID (ECAN Acceptance Filter n Standard Identifier)<br />
................................................................... 262<br />
CiRXFUL1 (ECAN Receive Buffer Full 1)................. 266<br />
CiRXFUL2 (ECAN Receive Buffer Full 2)................. 266<br />
CiRXMnEID (ECAN Acceptance Filter Mask n Extended<br />
Identifier) .......................................................... 265<br />
CiRXMnSID (ECAN Acceptance Filter Mask n Standard<br />
Identifier) .......................................................... 265<br />
CiRXOVF1 (ECAN Receive Buffer Overflow 1)........ 267<br />
CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 267<br />
CiTRBnSID (ECAN Buffer n Standard Identifier)..... 269,<br />
270, 272<br />
CiTRmnCON (ECAN TX/RX Buffer m Control) ........ 268<br />
CiVEC (ECAN Interrupt Code) ................................. 252<br />
CLKDIV (Clock Divisor) ............................................ 151<br />
CORCON (Core Control)...................................... 31, 96<br />
DFLTCON (QEI Control) .......................................... 226<br />
DMACS0 (DMA Controller Status 0) ........................ 140<br />
DMACS1 (DMA Controller Status 1) ........................ 142<br />
DMAxCNT (DMA Channel x Transfer Count)........... 139<br />
DMAxCON (DMA Channel x Control)....................... 136<br />
DMAxPAD (DMA Channel x Peripheral Address) .... 139<br />
DMAxREQ (DMA Channel x IRQ Select) ................. 137<br />
DMAxSTA (DMA Channel x RAM Start Address A) . 138<br />
DMAxSTB (DMA Channel x RAM Start Address B) . 138<br />
DSADR (Most Recent DMA RAM Address) ............. 143<br />
I2CxCON (I2Cx Control)........................................... 235<br />
I2CxMSK (I2Cx Slave Mode Address Mask)............ 239<br />
I2CxSTAT (I2Cx Status) ........................................... 237<br />
IFS0 (Interrupt Flag Status 0) ........................... 100, 107<br />
IFS1 (Interrupt Flag Status 1) ........................... 102, 109<br />
IFS2 (Interrupt Flag Status 2) ........................... 104, 111<br />
IFS3 (Interrupt Flag Status 3) ........................... 105, 112<br />
IFS4 (Interrupt Flag Status 4) ........................... 106, 113<br />
INTCON1 (Interrupt Control 1) ................................... 97<br />
INTCON2 (Interrupt Control 2) ................................... 99<br />
INTTREG Interrupt Control and Status Register ...... 131<br />
IPC0 (Interrupt Priority Control 0) ............................. 114<br />
IPC1 (Interrupt Priority Control 1) ............................. 115<br />
IPC11 (Interrupt Priority Control 11) ......................... 124<br />
IPC14 (Interrupt Priority Control 14) ......................... 125<br />
IPC15 (Interrupt Priority Control 15) ......................... 126<br />
IPC16 (Interrupt Priority Control 16) ......................... 127<br />
IPC17 (Interrupt Priority Control 17) ......................... 128<br />
IPC18 (Interrupt Priority Control 18) ................. 129, 130<br />
© 2011 Microchip Technology Inc. DS70291E-page 429