datasheet (3).pdf - EEWeb

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dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04 14.1 Input Capture Registers REGISTER 14-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER (x = 1, 2, 7 or 8) U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — ICSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-0, HC R-0, HC R/W-0 R/W-0 R/W-0 ICTMR ICI ICOV ICBNE ICM bit 7 bit 0 Legend: HC = Cleared in Hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 ICSIDL: Input Capture Module Stop in Idle Control bit 1 = Input capture module halts in CPU Idle mode 0 = Input capture module continues to operate in CPU Idle mode bit 12-8 Unimplemented: Read as ‘0’ bit 7 ICTMR: Input Capture Timer Select bits 1 = TMR2 contents are captured on capture event 0 = TMR3 contents are captured on capture event bit 6-5 ICI: Select Number of Captures per Interrupt bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred bit 3 ICBNE: Input Capture Buffer Empty Status bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty bit 2-0 ICM: Input Capture Mode Select bits 111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode (Rising edge detect only, all other control bits are not applicable). 110 = Unused (module disabled) 101 = Capture mode, every 16th rising edge 100 = Capture mode, every 4th rising edge 011 = Capture mode, every rising edge 010 = Capture mode, every falling edge 001 = Capture mode, every edge (rising and falling) (ICI bits do not control interrupt generation for this mode). 000 = Input capture module turned off DS70291E-page 204 © 2011 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04 15.0 OUTPUT COMPARE The Output Compare module can select either Timer2 Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 13. Output Compare” (DS70209) of the “dsPIC33F/ PIC24H Family Reference Manual”, 2: which is available from the Microchip web site (www.microchip.com). Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. FIGURE 15-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM 16 OCxRS OCxR Comparator 0 1 16 OCTSEL 0 1 TMR2 TMR3 TMR2 TMR3 Rollover Rollover or Timer3 for its time base. The module compares the value of the timer with the value of one or two compare registers depending on the operating mode selected. The state of the output pin changes when the timer value matches the compare register value. The Output Compare module generates either a single output pulse or a sequence of output pulses, by changing the state of the output pin on the compare match events. The Output Compare module can also generate interrupts on compare match events. The Output Compare module has multiple operating modes: • Active-Low One-Shot mode • Active-High One-Shot mode • Toggle mode • Delayed One-Shot mode • Continuous Pulse mode • PWM mode without fault protection • PWM mode with fault protection Output Logic 3 OCM Mode Select Set Flag bit OCxIF © 2011 Microchip Technology Inc. DS70291E-page 205 S R Q Output Enable Output Enable Logic OCx OCFA
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