datasheet (3).pdf - EEWeb

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
REGISTER 25-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER (1) (CONTINUED)
bit 7-0 CAL: RTC Drift Calibration bits
11111111 =Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute
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10000000 =Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute
01111111 =Maximum positive adjustment; adds 508 RTC clock pulses every one minute
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00000001 =Minimum positive adjustment; adds 4 RTC clock pulses every one minute
00000000 =No adjustment
Note 1: The RCFGCAL register is only affected by a POR.
2: A write to the RTCEN bit is only allowed when RTCWREN = 1.
3: This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register.
DS70291E-page 302 © 2011 Microchip Technology Inc.