Activity Report 2010 - CNRS

SCIENTIFIC REPORT
Fig. 5: Tunneling FET operating principle and schematics of the device. The TFET is made out a
gated PN diode: when the gate is biased at 0, no carrier can flow from drain to source because of
the wide tunnel barrier they have to flow through. But when the gate voltage is decreased the
barrier width is narrowed down allowing for band to band tunneling current.
FURTHER READING:
Appl. Phys. Lett. 94, 263508 (2009)
Tunneling field-effect transistor with
epitaxial junction in thin germanium-oninsulator
Microelectronic Engineering (2011)
Gate-induced drain leakage in FD-SOI
devices: What the TFET teaches us about the
MOSFET
6
Tunneling-based nano-FETs
Chair of Excellence 2008: Alex
ZASLAVSKY
Coordinator: Sorin CRISTOLOVEANU
(IMEP-LAHC).
The objective of this project is to
investigate the technological potential of
tunneling FETs (TFETs) built in
semiconductor-in-insulator technology to
complement or possibly replace standard
CMOS FETs in digital logic circuits. These
TFETs are theoretically predicted to
manifest sharper on-off characteristics
and higher I ON currents than Si
CMOSFETs.
If this theoretical promise is confirmed,
the technological insertion of such
devices is likely in the longer term, when
hybrid systems combining standard
CMOS logic with islands of alternative
technologies become standard. Also TFET
devices provide an experimental testbed
for interband tunneling (and other
quantum effects).
So far experimental demonstrations have
not fulfilled the theoretical expectations.
The originality of the approach of this
project is to combine advanced
technological fabrication with solid
modeling and characterization.
A emphasis is put on the comparison of
germanium-on-insulator (GeOI) TFETs
with their silicon-on-insulator (SOI)
counterparts in order to address high on
currents. Indeed there have been
already several reports of sub-60
mV/decade subthreshold slope in SOI
TFETs (including a world-leading result
from LETI-CEA) but at the expense of
relatively low I ON due to the large
bandgap of Si and insufficiently abrupt
junctions. Conversely, GeOI TFETs are
expected to have considerably larger I ON .
The project has already allowed to
experimentally demonstrate theoretical
calculations: interest of HfO 2 as high k
gate dielectric in order to improve the
subthreshold slope, interest of Ge to
increase the on current… The project has
lead to 3 publications in 2010 (ESSDERC,
JAP and APL) and some patents are
pending.
Fig.6: Alex ZASLAVSKY, Chair of Excellence
2008