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Compiler-specific Features<br />

0x00000004: f3ef8000 .... MRS r0,APSR ; formerly CPSR<br />

0x00000008: f00000080 .... AND r0,r0,#0x80<br />

0x0000000c: b672 r. CPSID i<br />

0x0000000e: 4770 pG BX lr<br />

In all cases, the __disable_irq intrinsic can only be executed in privileged modes, that<br />

is, in non user modes. In User mode this intrinsic does not change the interrupt flags in<br />

the CPSR.<br />

See also<br />

• __enable_irq.<br />

4.7.9 __enable_fiq<br />

This intrinsic enables FIQ interrupts.<br />

Note<br />

Typically, this intrinsic enables FIQ interrupts by clearing the F-bit in the CPSR.<br />

However, for v7-M, it clears the fault mask register (FAULTMASK). FIQ interrupts are<br />

not supported in v6-M.<br />

Syntax<br />

void __enable_fiq(void)<br />

Restrictions<br />

The __enable_fiq intrinsic can only be executed in privileged modes, that is, in non user<br />

modes. In User mode this intrinsic does not change the interrupt flags in the CPSR.<br />

See also<br />

• __disable_fiq on page 4-79.<br />

4.7.10 __enable_irq<br />

This intrinsic enables IRQ interrupts.<br />

Note<br />

Typically, this intrinsic enables IRQ interrupts by clearing the I-bit in the CPSR.<br />

However, for Cortex M-profile processors, it clears the exception mask register<br />

(PRIMASK).<br />

4-82 Copyright © 2007-2010 <strong>ARM</strong>. All rights reserved. <strong>ARM</strong> DUI 0348C<br />

Non-Confidential,<br />

ID101213

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