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Compiler-specific Features 4.7.83 __sxtb16 intrinsic This intrinsic inserts an SXTB16 instruction into the instruction stream generated by the compiler. It enables you to extract two 8-bit values from an operand and sign-extend them to 16 bits each. unsigned int __sxtb16(unsigned int val) Where val[7:0] and val[23:16] hold the two 8-bit values to be sign-extended. The __sxtb16 intrinsic returns the 8-bit values sign-extended to 16-bit values. Example: unsigned int sign_extend(unsigned int val) { unsigned int res; } res = __sxtb16(val1,val2); /* res[15:0] = SignExtended(val[7:0] res[31:16] = SignExtended(val[23:16] */ return res; See also • ARMv6 SIMD intrinsics on page 4-109 • Instruction summary on page 4-2 in the Assembler Guide • SXT, SXTA, UXT, and UXTA on page 4-109 in the Assembler Guide. 4-160 Copyright © 2007-2010 ARM. All rights reserved. ARM DUI 0348C Non-Confidential, ID101213
Compiler-specific Features 4.7.84 __uadd16 intrinsic This intrinsic inserts a UADD16 instruction into the instruction stream generated by the compiler. It enables you to perform two 16-bit unsigned integer additions. The GE bits in the APSR are set according to the results. unsigned int __uadd16(unsigned int val1, unsigned int val2) Where: val1 val2 holds the first two halfword summands for each addition holds the second two halfword summands for each addition. The __uadd16 intrinsic returns: • the addition of the low halfwords in each operand, in the low halfword of the return value • the addition of the high halfwords in each operand, in the high halfword of the return value. Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. If res is the return value, then: • if res[15:0] ≥ 0x10000 then APSR.GE[0] = 11 else 00 • if res[31:16] ≥ 0x10000 then APSR.GE[1] = 11 else 00. Example: unsigned int add_halfwords(unsigned int val1, unsigned int val2) { unsigned int res; } res = __uadd16(val1,val2); /* res[15:0] = val1[15:0] + val2[15:0] res[31:16] = val1[31:16] + val2[31:16] */ return res; See also • ARMv6 SIMD intrinsics on page 4-109 • Instruction summary on page 4-2 in the Assembler Guide • Parallel add and subtract on page 4-99 in the Assembler Guide. ARM DUI 0348C Copyright © 2007-2010 ARM. All rights reserved. 4-161 ID101213 Non-Confidential,
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® RealView Compilation Tools Versi
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Product Status The information in t
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Contents RealView Compilation Tools
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Preface This preface introduces the
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Preface Appendix A Via File Syntax
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Preface Other publications The foll
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Chapter 1 Introduction This chapter
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Introduction 1.2 Source language mo
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Introduction 1.3 Language extension
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Introduction • Compiling a C sour
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Chapter 2 Compiler Command-line Opt
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Compiler Command-line Options 2.1.2
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Compiler Command-line Options Each
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Compiler Command-line Options Note
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Language Extensions 3.1.2 #include_
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Appendix E Using NEON Support This
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Using NEON Support E.2 Vector data
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Using NEON Support • Vector long
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Using NEON Support uint64x1_t vqadd
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