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RealView Compilation Tools - ARM Information Center

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Compiler-specific Features<br />

4.7.44 <strong>ARM</strong>v6 SIMD intrinsics<br />

The <strong>ARM</strong> Architecture v6 Instruction Set Architecture adds many Single Instruction<br />

Multiple Data (SIMD) instructions to <strong>ARM</strong>v6 for the efficient software implementation<br />

of high-performance media applications.<br />

The <strong>ARM</strong> compiler supports intrinsics that map to the <strong>ARM</strong>v6 SIMD instructions.<br />

These intrinsics are available when compiling your code for an <strong>ARM</strong>v6 architecture or<br />

processor. If the chosen architecture does not support the <strong>ARM</strong>v6 SIMD instructions,<br />

compilation generates a warning and subsequent linkage fails with an undefined symbol<br />

reference.<br />

Note<br />

Each <strong>ARM</strong>v6 SIMD intrinsic is guaranteed to be compiled into a single, inline, machine<br />

instruction for an <strong>ARM</strong> v6 architecture or processor. However, the compiler might use<br />

optimized forms of underlying instructions when it detects opportunities to do so.<br />

The <strong>ARM</strong>v6 SIMD instructions can set the GE[3:0] bits in the Application Program<br />

Status Register (APSR). Some SIMD instructions update these flags to indicate the<br />

greater than or equal to status of each 8 or 16-bit slice of an SIMD operation.<br />

The <strong>ARM</strong> compiler treats the GE[3:0] bits as a global variable. To access these bits from<br />

within your C or C++ program, either:<br />

• access bits 16-19 of the APSR through a named register variable<br />

• use the __sel intrinsic to control a SEL instruction.<br />

See also<br />

Reference<br />

• <strong>ARM</strong>v6 SIMD intrinsics according to prefix on page 4-110<br />

• <strong>ARM</strong>v6 SIMD intrinsics, summary descriptions, byte lanes, side-effects on<br />

page 4-112<br />

• <strong>ARM</strong>v6 SIMD intrinsics, compatible processors and architectures on page 4-117<br />

• <strong>ARM</strong>v6 SIMD instruction intrinsics and APSR GE flags on page 4-118<br />

• <strong>ARM</strong>v6 SIMD instruction intrinsics by alphabetical listing on page 4-120<br />

• Named register variables on page 4-192<br />

• Registers on page 2-6 in the Assembler Guide<br />

• SEL on page 4-63 in the Assembler Guide<br />

• Chapter 5 NEON and VFP Programming in the Assembler Guide.<br />

<strong>ARM</strong> DUI 0348C Copyright © 2007-2010 <strong>ARM</strong>. All rights reserved. 4-109<br />

ID101213<br />

Non-Confidential,

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