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Using NEON Support E.3 Intrinsics The intrinsics described in this section map closely to NEON instructions. Each section begins with a list of function prototypes, with a comment specifying an equivalent assembler instruction. The compiler selects an instruction that has the required semantics, but there is no guarantee that the compiler produces the listed instruction. The intrinsics use a naming scheme that is similar to the NEON unified assembler syntax. That is, each intrinsic has the form: _ An additional q flag is provided to specify that the intrinsic operates on 128-bit vectors. For example: • vmul_s16, multiplies two vectors of signed 16-bit values. This compiles to VMUL.I16 d2, d0, d1. • vaddl_u8, is a long add of two 64-bit vectors containing unsigned 8-bit values, resulting in a 128-bit vector of unsigned 16-bit values. This compiles to VADDL.U8 q1, d0, d1. Note The intrinsic function prototypes in this section use the following type annotations: __const(n) the argument n must be a compile-time constant __constrange(min, max) the argument must be a compile-time constant in the range min to max __transfersize(n) the intrinsic loads n bytes from this pointer. Note The NEON intrinsic function prototypes that use __fp16 are only available for targets that have the NEON half-precision VFP extension. To enable use of __fp16, use the --fp16_format command-line option. See --fp16_format=format on page 2-59. E.3.1 Addition These intrinsics add vectors. Each lane in the result is the consequence of performing the addition on the corresponding lanes in each operand vector. The operations performed are as follows: • Vector add: vadd -> Vr[i]:=Va[i]+Vb[i] on page E-5 E-4 Copyright © 2007-2010 ARM. All rights reserved. ARM DUI 0348C Non-Confidential, ID101213
Using NEON Support • Vector long add: vadd -> Vr[i]:=Va[i]+Vb[i] • Vector wide add: vadd -> Vr[i]:=Va[i]+Vb[i] on page E-6 • Vector halving add: vhadd -> Vr[i]:=(Va[i]+Vb[i])>>1 on page E-6 • Vector rounding halving add: vrhadd -> Vr[i]:=(Va[i]+Vb[i]+1)>>1 on page E-6 • Vector saturating add: vqadd -> Vr[i]:=sat(Va[i]+Vb[i]) on page E-6 • Vector add high half -> Vr[i]:=Va[i]+Vb[i] on page E-7 • Vector rounding add high half on page E-7. Vector add: vadd -> Vr[i]:=Va[i]+Vb[i] Vr, Va, Vb have equal lane sizes. int8x8_t vadd_s8(int8x8_t a, int8x8_t b); // VADD.I8 d0,d0,d0 int16x4_t vadd_s16(int16x4_t a, int16x4_t b); // VADD.I16 d0,d0,d0 int32x2_t vadd_s32(int32x2_t a, int32x2_t b); // VADD.I32 d0,d0,d0 int64x1_t vadd_s64(int64x1_t a, int64x1_t b); // VADD.I64 d0,d0,d0 float32x2_t vadd_f32(float32x2_t a, float32x2_t b); // VADD.F32 d0,d0,d0 uint8x8_t vadd_u8(uint8x8_t a, uint8x8_t b); // VADD.I8 d0,d0,d0 uint16x4_t vadd_u16(uint16x4_t a, uint16x4_t b); // VADD.I16 d0,d0,d0 uint32x2_t vadd_u32(uint32x2_t a, uint32x2_t b); // VADD.I32 d0,d0,d0 uint64x1_t vadd_u64(uint64x1_t a, uint64x1_t b); // VADD.I64 d0,d0,d0 int8x16_t vaddq_s8(int8x16_t a, int8x16_t b); // VADD.I8 q0,q0,q0 int16x8_t vaddq_s16(int16x8_t a, int16x8_t b); // VADD.I16 q0,q0,q0 int32x4_t vaddq_s32(int32x4_t a, int32x4_t b); // VADD.I32 q0,q0,q0 int64x2_t vaddq_s64(int64x2_t a, int64x2_t b); // VADD.I64 q0,q0,q0 float32x4_t vaddq_f32(float32x4_t a, float32x4_t b); // VADD.F32 q0,q0,q0 uint8x16_t vaddq_u8(uint8x16_t a, uint8x16_t b); // VADD.I8 q0,q0,q0 uint16x8_t vaddq_u16(uint16x8_t a, uint16x8_t b); // VADD.I16 q0,q0,q0 uint32x4_t vaddq_u32(uint32x4_t a, uint32x4_t b); // VADD.I32 q0,q0,q0 uint64x2_t vaddq_u64(uint64x2_t a, uint64x2_t b); // VADD.I64 q0,q0,q0 Vector long add: vadd -> Vr[i]:=Va[i]+Vb[i] Va, Vb have equal lane sizes, result is a 128 bit vector of lanes that are twice the width. int16x8_t vaddl_s8(int8x8_t a, int8x8_t b); // VADDL.S8 q0,d0,d0 int32x4_t vaddl_s16(int16x4_t a, int16x4_t b); // VADDL.S16 q0,d0,d0 int64x2_t vaddl_s32(int32x2_t a, int32x2_t b); // VADDL.S32 q0,d0,d0 uint16x8_t vaddl_u8(uint8x8_t a, uint8x8_t b); // VADDL.U8 q0,d0,d0 uint32x4_t vaddl_u16(uint16x4_t a, uint16x4_t b); // VADDL.U16 q0,d0,d0 uint64x2_t vaddl_u32(uint32x2_t a, uint32x2_t b); // VADDL.U32 q0,d0,d0 ARM DUI 0348C Copyright © 2007-2010 ARM. All rights reserved. E-5 ID101213 Non-Confidential,
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Product Status The information in t
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Contents RealView Compilation Tools
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Preface This preface introduces the
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Preface Appendix A Via File Syntax
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Preface Other publications The foll
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Chapter 1 Introduction This chapter
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Introduction 1.2 Source language mo
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Introduction 1.3 Language extension
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Introduction • Compiling a C sour
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Chapter 2 Compiler Command-line Opt
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Compiler Command-line Options 2.1.2
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Compiler Command-line Options Each
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Compiler Command-line Options Note
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Compiler Command-line Options vfpv3
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Page 441 and 442: Appendix E Using NEON Support This
Page 443: Using NEON Support E.2 Vector data
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