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CHAPTER 8 WATCHDOG TIMER8.4.2 Operation as interval timerWhen bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1,respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at an intervalspecified by a preset count value.Select a count clock (or interval time) by setting bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clockselection register (WDCS). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 ofWDTM) is set to 1.In interval timer mode, the interrupt mask flag (WDTMK) is valid, and a maskable interrupt (INTWDT) can begenerated. The priority of INTWDT is set as the highest of all the maskable interrupts.The interval timer continues operation in HALT mode, but stops in STOP mode. Therefore, first set RUN to 1 toclear the interval timer before executing the STOP instruction.Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when watchdog timer mode is selected), intervaltimer mode is not set unless a RESET signal is input.2. The interval time may be up to 0.8% shorter than the set time when WDTM has just been set.Table 8-5. Interval Generated Using Interval TimerWDCS2 WDCS1 WDCS0 Interval Time At fX = 10.0 MHz Operation Note At fX = 5.0 MHz Operation0 0 0 2 11 × 1/fX 205 µs 410 µs0 1 0 2 13 × 1/fX 819 µs 1.64 ms1 0 0 2 15 × 1/fX 3.28 ms 6.55 ms1 1 0 2 17 × 1/fX 13.1 ms 26.2 msNote Expanded-specification products only.RemarkfX: System clock oscillation frequency114User’s Manual U14801EJ3V1<strong>UD</strong>
CHAPTER 9 SERIAL INTERFACE 209.1 Functions of Serial Interface 20Serial interface 20 has the following three modes.• Operation stop mode• Asynchronous serial interface (UART) mode• 3-wire serial I/O mode(1) Operation stop modeThis mode is used when serial transfer is not performed. Power consumption is minimized in this mode.(2) Asynchronous serial interface (UART) modeThis mode is used to send and receive the one byte of data that follows a start bit. It supports full-duplexcommunication.Serial interface 20 contains a UART-dedicated baud rate generator, enabling communication over a widerange of baud rates. It is also possible to define baud rates by dividing the frequency of the clock input to theASCK20 pin.(3) 3-wire serial I/O mode (switchable between MSB-first and LSB-first transmission)This mode is used to transmit 8-bit data, using three lines: a serial clock (SCK20) line and two serial datalines (SI20 and SO20).As it supports simultaneous transmission and reception, 3-wire serial I/O mode requires less processing timefor data transmission than asynchronous serial interface mode.Because, in 3-wire serial I/O mode, it is possible to select whether 8-bit data transmission begins with theMSB or LSB, serial interface 20 can be connected to any device regardless of whether that device isdesigned for MSB-first or LSB-first transmission.3-wire serial I/O mode is useful for connecting peripheral I/O circuits and display controllers havingconventional synchronous serial interfaces, such as those of the 75X/XL, 78K, and 17K Series devices.9.2 Configuration of Serial Interface 20Serial interface 20 includes the following hardware.Table 9-1. Configuration of Serial Interface 20ItemConfigurationRegistersControl registersTransmission shift register 20 (TXS20)Reception shift register 20 (RXS20)Receive buffer register 20 (RXB20)Serial operation mode register 20 (CSIM20)Asynchronous serial interface mode register 20 (ASIM20)Asynchronous serial interface status register 20 (ASIS20)Baud rate generator control register 20 (BRGC20)Port mode register 2 (PM2)Port 2 (P2)User’s Manual U14801EJ3V1<strong>UD</strong> 115
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User’s ManualµPD789074 Subseries
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NOTES FOR CMOS DEVICES1VOLTAGE APPL
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Regional InformationSome informatio
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INTRODUCTIONReadersPurposeOrganizat
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Documents for Flash Memory WritingP
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CHAPTER 11 STANDBY FUNCTION .......
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LIST OF FIGURES (1/3)Figure No. Tit
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LIST OF FIGURES (3/3)Figure No. Tit
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LIST OF TABLES (2/2)Table No. Title
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CHAPTER 1 GENERAL1.2 Features• RO
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CHAPTER 1 GENERAL1.6 Pin Configurat
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CHAPTER 1 GENERALThe major function
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CHAPTER 1 GENERAL1.8 Block DiagramT
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CHAPTER 1 GENERAL1.10 Differences B
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CHAPTER 2 PIN FUNCTIONS(2) Non-port
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CHAPTER 2 PIN FUNCTIONS(h) RxD20, T
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CHAPTER 2 PIN FUNCTIONS2.3 Pin I/O
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CHAPTER 3 CPU ARCHITECTURE3.1 Memor
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CHAPTER 3 CPU ARCHITECTUREFigure 3-
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CHAPTER 3 CPU ARCHITECTURE3.1.1 Int
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CHAPTER 3 CPU ARCHITECTURE(a) Inter
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CHAPTER 3 CPU ARCHITECTURE3.2.2 Gen
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CHAPTER 3 CPU ARCHITECTURETable 3-3
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CHAPTER 3 CPU ARCHITECTURE3.3 Instr
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CHAPTER 3 CPU ARCHITECTURE3.3.3 Tab
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CHAPTER 3 CPU ARCHITECTURE3.4.2 Sho
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CHAPTER 3 CPU ARCHITECTURE3.4.4 Reg
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CHAPTER 3 CPU ARCHITECTURE3.4.6 Bas
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Page 79 and 80: CHAPTER 5 CLOCK GENERATORFigure 5-4
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Page 83 and 84: Figure 6-1. Block Diagram of 16-Bit
Page 85 and 86: CHAPTER 6 16-BIT TIMER 906.3 Contro
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CHAPTER 11 STANDBY FUNCTION11.1 Sta
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CHAPTER 11 STANDBY FUNCTION11.2 Ope
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CHAPTER 11 STANDBY FUNCTION11.2.2 S
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CHAPTER 12 RESET FUNCTIONThe follow
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CHAPTER 12 RESET FUNCTIONTable 12-1
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CHAPTER 13 µPD78F907613.1 Flash Me
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CHAPTER 13 µPD78F9076Figure 13-3.
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CHAPTER 13 µPD78F907613.1.3 On-boa
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CHAPTER 13 µPD78F9076When the rese
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CHAPTER 13 µPD78F9076Figure 13-9.
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CHAPTER 14 INSTRUCTION SET OVERVIEW
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CHAPTER 15 ELECTRICAL SPECIFICATION
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CHAPTER 18 RECOMMENDED SOLDERING CO
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APPENDIX A DEVELOPMENT TOOLSThe fol
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APPENDIX A DEVELOPMENT TOOLSA.1 Sof
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APPENDIX A DEVELOPMENT TOOLSA.4 Fla
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APPENDIX B NOTES ON TARGET SYSTEM D
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APPENDIX C REGISTER INDEXC.1 Regist
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APPENDIX C REGISTER INDEXC.2 Regist
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APPENDIX D REVISION HISTORYThe foll
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