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CHAPTER 11 STANDBY FUNCTION11.1.2 Standby function control registerThe wait time after STOP mode is released upon interrupt request until the oscillation stabilizes is controlled withthe oscillation stabilization time selection register (OSTS).OSTS is set with an 8-bit memory manipulation instruction.RESET input sets OSTS to 04H. However, the oscillation stabilization time after RESET input is 2 15 /fX, instead of2 17 /fX.Figure 11-1. Format of Oscillation Stabilization Time Selection RegisterSymbol 7 6 5 4 3 2 1 0 Address After reset R/WOSTS0 0 0 0 0 OSTS2 OSTS1 OSTS0FFFAH 04H R/WOSTS2OSTS1OSTS0Oscillation stabilization time selectionAt fX = 10.0 MHz operation NoteAt fX = 5.0 MHz operation0002 12 /fX410 µ s819 µ s0102 15 /fX3.28 ms6.55 ms1002 17 /fX13.1 ms26.2 msOther than aboveSetting prohibitedNote Expanded-specification products only.Caution The wait time after STOP mode is released does not include the time from STOP mode releaseto clock oscillation start ("a" in the figure below), regardless of whether STOP mode is releasedby RESET input or by interrupt generation.STOP mode releaseX1 pin voltageWaveformaRemarkfX: System clock oscillation frequency166User’s Manual U14801EJ3V1<strong>UD</strong>
CHAPTER 11 STANDBY FUNCTION11.2 Operation of Standby Function11.2.1 HALT mode(1) HALT modeHALT mode is set by executing the HALT instruction.The operation statuses in HALT mode are shown in the following table.Table 11-1. Operation Statuses in HALT ModeItemSystem clock generatorCPUPort (output latch)16-bit timer 908-bit timer/event counter 80Watchdog timerSerial interface 20External interruptHALT Mode Operation StatusSystem clock oscillation enabledClock supply to CPU stoppedOperation disabledRemains in the state existing before the selection of HALT modeOperation enabledOperation enabledOperation enabledOperation enabledOperation enabled NoteNote Maskable interrupt that is not masked(2) Releasing HALT modeHALT mode can be released by the following three sources.(a) Releasing by unmasked interrupt requestHALT mode is released by an unmasked interrupt request. In this case, if interrupt requestacknowledgment is enabled, vectored interrupt servicing is performed. If interrupt acknowledgment isdisabled, the instruction at the next address is executed.Figure 11-2. Releasing HALT Mode by InterruptHALTinstructionWaitStandbyrelease signalOperatingmodeHALT modeWaitOperating modeClockOscillationRemarks 1. The broken lines indicate the case where the interrupt request that has released standbymode is acknowledged.2. The wait time is as follows.• When vectored interrupt servicing is performed: 9 to 10 clocks• When vectored interrupt servicing is not performed: 1 to 2 clocksUser’s Manual U14801EJ3V1<strong>UD</strong> 167
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User’s ManualµPD789074 Subseries
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NOTES FOR CMOS DEVICES1VOLTAGE APPL
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Regional InformationSome informatio
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INTRODUCTIONReadersPurposeOrganizat
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Documents for Flash Memory WritingP
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CHAPTER 11 STANDBY FUNCTION .......
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LIST OF FIGURES (1/3)Figure No. Tit
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LIST OF FIGURES (3/3)Figure No. Tit
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LIST OF TABLES (2/2)Table No. Title
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CHAPTER 1 GENERAL1.2 Features• RO
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CHAPTER 1 GENERAL1.6 Pin Configurat
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CHAPTER 1 GENERALThe major function
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CHAPTER 1 GENERAL1.8 Block DiagramT
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CHAPTER 1 GENERAL1.10 Differences B
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CHAPTER 2 PIN FUNCTIONS(2) Non-port
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CHAPTER 2 PIN FUNCTIONS(h) RxD20, T
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CHAPTER 2 PIN FUNCTIONS2.3 Pin I/O
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CHAPTER 3 CPU ARCHITECTURE3.1 Memor
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CHAPTER 3 CPU ARCHITECTUREFigure 3-
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CHAPTER 3 CPU ARCHITECTURE3.1.1 Int
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CHAPTER 3 CPU ARCHITECTURE(a) Inter
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CHAPTER 3 CPU ARCHITECTURE3.2.2 Gen
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CHAPTER 3 CPU ARCHITECTURETable 3-3
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CHAPTER 3 CPU ARCHITECTURE3.3 Instr
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CHAPTER 3 CPU ARCHITECTURE3.3.3 Tab
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CHAPTER 3 CPU ARCHITECTURE3.4.2 Sho
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CHAPTER 3 CPU ARCHITECTURE3.4.4 Reg
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CHAPTER 3 CPU ARCHITECTURE3.4.6 Bas
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CHAPTER 4 PORT FUNCTIONSTable 4-1.
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CHAPTER 4 PORT FUNCTIONS4.2.2 Port
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CHAPTER 4 PORT FUNCTIONSFigure 4-5.
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CHAPTER 4 PORT FUNCTIONSFigure 4-7.
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CHAPTER 4 PORT FUNCTIONS4.3 Port Fu
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CHAPTER 4 PORT FUNCTIONS(3) Pull-up
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CHAPTER 5 CLOCK GENERATOR5.1 Clock
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CHAPTER 5 CLOCK GENERATOR5.4 System
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CHAPTER 5 CLOCK GENERATORFigure 5-4
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CHAPTER 5 CLOCK GENERATOR5.6 Changi
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Figure 6-1. Block Diagram of 16-Bit
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CHAPTER 6 16-BIT TIMER 906.3 Contro
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CHAPTER 6 16-BIT TIMER 90(2) Buzzer
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CHAPTER 6 16-BIT TIMER 906.4 Operat
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CHAPTER 6 16-BIT TIMER 906.4.2 Oper
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CHAPTER 6 16-BIT TIMER 906.4.4 16-b
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CHAPTER 6 16-BIT TIMER 906.5 Notes
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER
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CHAPTER 8 WATCHDOG TIMER8.1 Watchdo
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CHAPTER 16 ELECTRICAL SPECIFICATION
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CHAPTER 18 RECOMMENDED SOLDERING CO
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APPENDIX A DEVELOPMENT TOOLSThe fol
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APPENDIX A DEVELOPMENT TOOLSA.1 Sof
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APPENDIX A DEVELOPMENT TOOLSA.4 Fla
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APPENDIX B NOTES ON TARGET SYSTEM D
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APPENDIX C REGISTER INDEXC.1 Regist
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APPENDIX C REGISTER INDEXC.2 Regist
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APPENDIX D REVISION HISTORYThe foll
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uPD789074 Subseries 8-Bit Single-Chip Microcontrollers UD - Home

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