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CHAPTER 9 SERIAL INTERFACE 20(c) Baud rate generator control register 20 (BRGC20)BRGC20 is set with an 8-bit memory manipulation instruction.RESET input clears BRGC20 to 00H.Symbol 7 6 5 4 3 2 1 0 Address After reset R/WBRGC20TPS203 TPS202 TPS201 TPS200 0 0 0 0FF73H 00H R/WTPS203TPS202TPS201TPS200Selection of source clock for baud rate generatornAt fX = 10.0 MHz operation NoteAt fX = 5.0 MHz operation0000fX/25.0 MHz2.5 MHz10001fX/2 22.5 MHz1.25 MHz20010fX/2 31.25 MHz625 kHz30011fX/2 4625 kHz313 kHz40100fX/2 5313 kHz156 kHz50101fX/2 6156 kHz78.1 kHz60110fX/2 778.1 kHz39.1 kHz70111fX/2 839.1 kHz19.5 kHz8Other than aboveSetting prohibitedNote Expanded-specification products only.Cautions 1. When writing to BRGC20 is performed during a communication operation, the baudrate generator output is disrupted and communication cannot be performednormally. Be sure not to write to BRGC20 during a communication operation.2. Be sure not to select n = 1 during operation at fX > 5.0 MHz in 3-wire serial I/O modebecause the resulting serial clock exceeds the rated range.3. When the external input clock is selected, set port mode register 2 (PM2) to inputmode.Remarks 1. fX: System clock oscillation frequency2. n: Value determined by setting TPS200 through TPS203 (1 ≤ n ≤ 8)If the internal clock is used as the serial clock for 3-wire serial I/O mode, set bits TPS200 to TPS203 toset the frequency of the serial clock. To obtain the frequency to be set, use the following expression.When an external serial clock is used, setting BRGC20 is not necessary.Serial clock frequency =fX2 n + 1[Hz]fX: System clock oscillation frequencyn: Value determined by setting TPS200 to TPS203 as shown in the above table (1 ≤ n ≤ 8)142User’s Manual U14801EJ3V1<strong>UD</strong>
CHAPTER 9 SERIAL INTERFACE 20(2) Communication operationIn 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data istransmitted/received bit by bit in synchronization with the serial clock.Transmit shift register 20 (TXS20/SIO20) and receive shift register 20 (RXS20) shift operations areperformed in synchronization with the fall of the serial clock (SCK20). Then transmit data is held in the SO20latch and output from the SO20 pin. Also, receive data input to the SI20 pin is latched in receive bufferregister 20 (RXB20/SIO20) on the rise of SCK20.At the end of an 8-bit transfer, the operation of TXS20/SIO20 and RXS20 stops automatically, and theinterrupt request signal (INTCSI20) is generated.Figure 9-11. 3-Wire Serial I/O Mode Timing (1/7)(i) Master operation timing (when DAP20 = 0, CKP20 = 0, SSE20 = 0)SIO20WriteSCK201 2 3 4 5 6 7 8SO20NoteDO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0SI20DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0INTCSI20Note The value of the last bit previously output is output.User’s Manual U14801EJ3V1<strong>UD</strong> 143
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User’s ManualµPD789074 Subseries
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NOTES FOR CMOS DEVICES1VOLTAGE APPL
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Regional InformationSome informatio
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INTRODUCTIONReadersPurposeOrganizat
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Documents for Flash Memory WritingP
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CHAPTER 11 STANDBY FUNCTION .......
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LIST OF FIGURES (1/3)Figure No. Tit
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LIST OF FIGURES (3/3)Figure No. Tit
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LIST OF TABLES (2/2)Table No. Title
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CHAPTER 1 GENERAL1.2 Features• RO
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CHAPTER 1 GENERAL1.6 Pin Configurat
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CHAPTER 1 GENERALThe major function
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CHAPTER 1 GENERAL1.8 Block DiagramT
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CHAPTER 1 GENERAL1.10 Differences B
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CHAPTER 2 PIN FUNCTIONS(2) Non-port
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CHAPTER 2 PIN FUNCTIONS(h) RxD20, T
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CHAPTER 2 PIN FUNCTIONS2.3 Pin I/O
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CHAPTER 3 CPU ARCHITECTURE3.1 Memor
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CHAPTER 3 CPU ARCHITECTUREFigure 3-
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CHAPTER 3 CPU ARCHITECTURE3.1.1 Int
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CHAPTER 3 CPU ARCHITECTURE(a) Inter
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CHAPTER 3 CPU ARCHITECTURE3.2.2 Gen
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CHAPTER 3 CPU ARCHITECTURETable 3-3
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CHAPTER 3 CPU ARCHITECTURE3.3 Instr
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CHAPTER 3 CPU ARCHITECTURE3.3.3 Tab
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CHAPTER 3 CPU ARCHITECTURE3.4.2 Sho
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CHAPTER 3 CPU ARCHITECTURE3.4.4 Reg
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CHAPTER 3 CPU ARCHITECTURE3.4.6 Bas
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CHAPTER 4 PORT FUNCTIONSTable 4-1.
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CHAPTER 4 PORT FUNCTIONS4.2.2 Port
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CHAPTER 4 PORT FUNCTIONSFigure 4-5.
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CHAPTER 4 PORT FUNCTIONSFigure 4-7.
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CHAPTER 4 PORT FUNCTIONS4.3 Port Fu
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CHAPTER 4 PORT FUNCTIONS(3) Pull-up
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CHAPTER 5 CLOCK GENERATOR5.1 Clock
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CHAPTER 5 CLOCK GENERATOR5.4 System
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CHAPTER 5 CLOCK GENERATORFigure 5-4
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CHAPTER 5 CLOCK GENERATOR5.6 Changi
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Figure 6-1. Block Diagram of 16-Bit
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CHAPTER 6 16-BIT TIMER 906.3 Contro
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CHAPTER 6 16-BIT TIMER 90(2) Buzzer
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CHAPTER 6 16-BIT TIMER 906.4 Operat
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CHAPTER 14 INSTRUCTION SET OVERVIEW
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CHAPTER 15 ELECTRICAL SPECIFICATION
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CHAPTER 18 RECOMMENDED SOLDERING CO
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APPENDIX A DEVELOPMENT TOOLSThe fol
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APPENDIX A DEVELOPMENT TOOLSA.1 Sof
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APPENDIX A DEVELOPMENT TOOLSA.4 Fla
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APPENDIX B NOTES ON TARGET SYSTEM D
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APPENDIX C REGISTER INDEXC.1 Regist
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APPENDIX C REGISTER INDEXC.2 Regist
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APPENDIX D REVISION HISTORYThe foll
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uPD789074 Subseries 8-Bit Single-Chip Microcontrollers UD - Home

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