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CHAPTER 9 SERIAL INTERFACE 20(b) Parity types and operationThe parity bit is used to detect a bit error in the communication data. Normally, the same kind of paritybit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit(odd number) error can be detected. With 0 parity and no parity, an error cannot be detected.(i) Even parity• At transmissionThe parity bit is determined so that the number of bits with a value of "1" in the transmit dataincluding the parity bit is even. The parity bit value should be as follows.The number of bits with a value of "1" is an odd number in transmit data: 1The number of bits with a value of "1" is an even number in transmit data: 0• At receptionThe number of bits with a value of "1" in the receive data including the parity bit is counted, and ifthe number is odd, a parity error occurs.(ii) Odd parity• At transmissionConversely to even parity, the parity bit is determined so that the number of bits with a value of "1"in the transmit data including the parity bit is odd. The parity bit value should be as follows.The number of bits with a value of "1" is an odd number in transmit data: 0The number of bits with a value of "1" is an even number in transmit data: 1• At receptionThe number of bits with a value of "1" in the receive data including the parity bit is counted, and ifthe number is even, a parity error occurs.(iii) 0 parityWhen transmitting, the parity bit is set to "0" irrespective of the transmit data.At reception, a parity bit check is not performed. Therefore, a parity error does not occur,irrespective of whether the parity bit is set to "0" or "1".(iv) No parityA parity bit is not added to the transmit data.At reception, data is received assuming that there is no parity bit. Since there is no parity bit, aparity error does not occur.134User’s Manual U14801EJ3V1<strong>UD</strong>
CHAPTER 9 SERIAL INTERFACE 20(c) TransmissionA transmit operation is started by writing transmit data to transmit shift register 20 (TXS20). The startbit, parity bit, and stop bit(s) are added automatically.When the transmit operation starts, the data in TXS20 is shifted out, and when TXS20 is empty, atransmission completion interrupt (INTST20) is generated.Figure 9-8. Asynchronous Serial Interface Transmission Completion Interrupt Timing(a) Stop bit length: 1TxD20 (Output)D0D1D2D6D7ParitySTOPSTARTINTST20(b) Stop bit length: 2TxD20 (Output)D0D1D2D6D7ParitySTOPSTARTINTST20Caution Do not rewrite asynchronous serial interface mode register 20 (ASIM20) during atransmit operation. If the ASIM20 register is rewritten during transmission,subsequent transmission may not be performed (the normal state is restored byRESET input).It is possible to determine whether transmission is in progress by software by using atransmission completion interrupt (INTST20) or the interrupt request flag (STIF20) setby INTST20.User’s Manual U14801EJ3V1<strong>UD</strong> 135
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User’s ManualµPD789074 Subseries
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NOTES FOR CMOS DEVICES1VOLTAGE APPL
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Regional InformationSome informatio
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INTRODUCTIONReadersPurposeOrganizat
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Documents for Flash Memory WritingP
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CHAPTER 11 STANDBY FUNCTION .......
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LIST OF FIGURES (1/3)Figure No. Tit
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LIST OF FIGURES (3/3)Figure No. Tit
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LIST OF TABLES (2/2)Table No. Title
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CHAPTER 1 GENERAL1.2 Features• RO
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CHAPTER 1 GENERAL1.6 Pin Configurat
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CHAPTER 1 GENERALThe major function
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CHAPTER 1 GENERAL1.8 Block DiagramT
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CHAPTER 1 GENERAL1.10 Differences B
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CHAPTER 2 PIN FUNCTIONS(2) Non-port
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CHAPTER 2 PIN FUNCTIONS(h) RxD20, T
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CHAPTER 2 PIN FUNCTIONS2.3 Pin I/O
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CHAPTER 3 CPU ARCHITECTURE3.1 Memor
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CHAPTER 3 CPU ARCHITECTUREFigure 3-
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CHAPTER 3 CPU ARCHITECTURE3.1.1 Int
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CHAPTER 3 CPU ARCHITECTURE(a) Inter
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CHAPTER 3 CPU ARCHITECTURE3.2.2 Gen
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CHAPTER 3 CPU ARCHITECTURETable 3-3
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CHAPTER 3 CPU ARCHITECTURE3.3 Instr
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CHAPTER 3 CPU ARCHITECTURE3.3.3 Tab
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CHAPTER 3 CPU ARCHITECTURE3.4.2 Sho
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CHAPTER 3 CPU ARCHITECTURE3.4.4 Reg
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CHAPTER 3 CPU ARCHITECTURE3.4.6 Bas
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CHAPTER 4 PORT FUNCTIONSTable 4-1.
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CHAPTER 4 PORT FUNCTIONS4.2.2 Port
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CHAPTER 4 PORT FUNCTIONSFigure 4-5.
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CHAPTER 4 PORT FUNCTIONSFigure 4-7.
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CHAPTER 4 PORT FUNCTIONS4.3 Port Fu
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CHAPTER 4 PORT FUNCTIONS(3) Pull-up
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CHAPTER 5 CLOCK GENERATOR5.1 Clock
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CHAPTER 5 CLOCK GENERATOR5.4 System
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CHAPTER 5 CLOCK GENERATORFigure 5-4
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CHAPTER 5 CLOCK GENERATOR5.6 Changi
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CHAPTER 14 INSTRUCTION SET OVERVIEW
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CHAPTER 15 ELECTRICAL SPECIFICATION
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CHAPTER 18 RECOMMENDED SOLDERING CO
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APPENDIX A DEVELOPMENT TOOLSThe fol
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APPENDIX A DEVELOPMENT TOOLSA.1 Sof
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APPENDIX A DEVELOPMENT TOOLSA.4 Fla
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APPENDIX B NOTES ON TARGET SYSTEM D
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APPENDIX C REGISTER INDEXC.1 Regist
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APPENDIX C REGISTER INDEXC.2 Regist
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APPENDIX D REVISION HISTORYThe foll
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uPD789074 Subseries 8-Bit Single-Chip Microcontrollers UD - Home

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