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CHAPTER 10 INTERRUPT FUNCTIONS(3) External interrupt mode register 0 (INTM0)INTM0 is used to specify a valid edge for INTP0 to INTP2.INTM0 is set with an 8-bit memory manipulation instruction.RESET input clears INTM0 to 00H.Figure 10-4. Format of External Interrupt Mode Register 0Symbol 7 6 5 4 3 2 1 0 Address After reset R/WINTM0ES21 ES20 ES11 ES10 ES01 ES00 0 0FFECH 00H R/WES21ES20INTP2 valid edge selection00110101Falling edgeRising edgeSetting prohibitedBoth rising and falling edgesES11ES10INTP1 valid edge selection00110101Falling edgeRising edgeSetting prohibitedBoth rising and falling edgesES01ES00INTP0 valid edge selection00110101Falling edgeRising edgeSetting prohibitedBoth rising and falling edgesCautions 1. Bits 0 and 1 must both be set to 0.2. Before setting INTM0, set the corresponding interrupt mask flag to 1 to disableinterrupts.To enable interrupts, clear to 0 the corresponding interrupt request flag, then thecorresponding interrupt mask flag.156User’s Manual U14801EJ3V1UD
CHAPTER 10 INTERRUPT FUNCTIONS(4) Program status word (PSW)The program status word is used to hold the instruction execution result and the current status of theinterrupt requests. The IE flag, used to enable and disable maskable interrupts, is mapped to the PSW.The PSW can be read- and write-accessed in 8-bit units, as well as using bit manipulation instructions anddedicated instructions (EI and DI). When a vector interrupt is acknowledged, the PSW is automaticallysaved to a stack, and the IE flag is reset to 0.RESET input sets PSW to 02H.Figure 10-5. Program Status Word ConfigurationSymbolPSW7 6 5 4 3 2 1 0IE Z 0 AC 0 0 1 CYAfter reset02HUsed in the execution of ordinary instructionsIEWhether to enable/disable interrupt acknowledgment01DisabledEnabledUser’s Manual U14801EJ3V1UD 157
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User’s ManualµPD789074 Subseries
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NOTES FOR CMOS DEVICES1VOLTAGE APPL
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Regional InformationSome informatio
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INTRODUCTIONReadersPurposeOrganizat
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Documents for Flash Memory WritingP
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CHAPTER 11 STANDBY FUNCTION .......
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LIST OF FIGURES (1/3)Figure No. Tit
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LIST OF FIGURES (3/3)Figure No. Tit
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LIST OF TABLES (2/2)Table No. Title
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CHAPTER 1 GENERAL1.2 Features• RO
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CHAPTER 1 GENERAL1.6 Pin Configurat
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CHAPTER 1 GENERALThe major function
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CHAPTER 1 GENERAL1.8 Block DiagramT
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CHAPTER 1 GENERAL1.10 Differences B
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CHAPTER 2 PIN FUNCTIONS(2) Non-port
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CHAPTER 2 PIN FUNCTIONS(h) RxD20, T
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CHAPTER 2 PIN FUNCTIONS2.3 Pin I/O
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CHAPTER 3 CPU ARCHITECTURE3.1 Memor
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CHAPTER 3 CPU ARCHITECTUREFigure 3-
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CHAPTER 3 CPU ARCHITECTURE3.1.1 Int
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CHAPTER 3 CPU ARCHITECTURE(a) Inter
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CHAPTER 3 CPU ARCHITECTURE3.2.2 Gen
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CHAPTER 3 CPU ARCHITECTURETable 3-3
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CHAPTER 3 CPU ARCHITECTURE3.3 Instr
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CHAPTER 3 CPU ARCHITECTURE3.3.3 Tab
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CHAPTER 3 CPU ARCHITECTURE3.4.2 Sho
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CHAPTER 3 CPU ARCHITECTURE3.4.4 Reg
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CHAPTER 3 CPU ARCHITECTURE3.4.6 Bas
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CHAPTER 4 PORT FUNCTIONSTable 4-1.
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CHAPTER 4 PORT FUNCTIONS4.2.2 Port
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CHAPTER 4 PORT FUNCTIONSFigure 4-5.
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CHAPTER 4 PORT FUNCTIONSFigure 4-7.
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CHAPTER 4 PORT FUNCTIONS4.3 Port Fu
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CHAPTER 4 PORT FUNCTIONS(3) Pull-up
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CHAPTER 5 CLOCK GENERATOR5.1 Clock
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CHAPTER 5 CLOCK GENERATOR5.4 System
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CHAPTER 5 CLOCK GENERATORFigure 5-4
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CHAPTER 5 CLOCK GENERATOR5.6 Changi
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Figure 6-1. Block Diagram of 16-Bit
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CHAPTER 6 16-BIT TIMER 906.3 Contro
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CHAPTER 6 16-BIT TIMER 90(2) Buzzer
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CHAPTER 6 16-BIT TIMER 906.4 Operat
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CHAPTER 6 16-BIT TIMER 906.4.2 Oper
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CHAPTER 6 16-BIT TIMER 906.4.4 16-b
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CHAPTER 6 16-BIT TIMER 906.5 Notes
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER
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CHAPTER 15 ELECTRICAL SPECIFICATION
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CHAPTER 18 RECOMMENDED SOLDERING CO
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APPENDIX A DEVELOPMENT TOOLSThe fol
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APPENDIX A DEVELOPMENT TOOLSA.1 Sof
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APPENDIX A DEVELOPMENT TOOLSA.4 Fla
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APPENDIX B NOTES ON TARGET SYSTEM D
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APPENDIX C REGISTER INDEXC.1 Regist
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APPENDIX C REGISTER INDEXC.2 Regist
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APPENDIX D REVISION HISTORYThe foll
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uPD789074 Subseries 8-Bit Single-Chip Microcontrollers UD - Home

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