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CHAPTER 10 INTERRUPT FUNCTIONS10.4.2 Maskable interrupt request acknowledgment operationA maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and thecorresponding interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in the interruptenabled status (when the IE flag is set to 1).The time required to start the interrupt servicing after a maskable interrupt request has been generated is shownin Table 10-3.See Figures 10-10 and 10-11 for the interrupt request acknowledgment timing.Table 10-3. Time from Generation of Maskable Interrupt Request to ServicingMinimum TimeMaximum Time Note9 clocks 19 clocksNote The wait time is maximum when an interruptrequest is generated immediately before BT andBF instruction.1Remark 1 clock: (fCPU: CPU clock)fCPUWhen two or more maskable interrupt requests are generated at the same time, they are acknowledged startingfrom the interrupt request assigned the highest priority.A pending interrupt is acknowledged when a status in which it can be acknowledged is set.Figure 10-9 shows the algorithm of interrupt requests acknowledgment.When a maskable interrupt request is acknowledged, the contents of the PSW and PC are saved to the stack inthat order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded tothe PC, and execution branches.To return from interrupt servicing, use the RETI instruction.160User’s Manual U14801EJ3V1<strong>UD</strong>
CHAPTER 10 INTERRUPT FUNCTIONSFigure 10-9. Interrupt Request Acknowledgment Processing AlgorithmStartNo××IF = 1 ?Yes (Interrupt request generated)××MK = 0 ?NoYesInterrupt request pendingIE = 1 ?NoYesVectored interruptservicingInterrupt request pending××IF:××MK:IE:Interrupt request flagInterrupt mask flagFlag to control maskable interrupt request acknowledgment (1 = enable, 0 = disable)User’s Manual U14801EJ3V1<strong>UD</strong> 161
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User’s ManualµPD789074 Subseries
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NOTES FOR CMOS DEVICES1VOLTAGE APPL
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Regional InformationSome informatio
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INTRODUCTIONReadersPurposeOrganizat
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Documents for Flash Memory WritingP
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CHAPTER 11 STANDBY FUNCTION .......
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LIST OF FIGURES (1/3)Figure No. Tit
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LIST OF FIGURES (3/3)Figure No. Tit
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LIST OF TABLES (2/2)Table No. Title
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CHAPTER 1 GENERAL1.2 Features• RO
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CHAPTER 1 GENERAL1.6 Pin Configurat
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CHAPTER 1 GENERALThe major function
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CHAPTER 1 GENERAL1.8 Block DiagramT
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CHAPTER 1 GENERAL1.10 Differences B
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CHAPTER 2 PIN FUNCTIONS(2) Non-port
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CHAPTER 2 PIN FUNCTIONS(h) RxD20, T
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CHAPTER 2 PIN FUNCTIONS2.3 Pin I/O
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CHAPTER 3 CPU ARCHITECTURE3.1 Memor
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CHAPTER 3 CPU ARCHITECTUREFigure 3-
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CHAPTER 3 CPU ARCHITECTURE3.1.1 Int
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CHAPTER 3 CPU ARCHITECTURE(a) Inter
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CHAPTER 3 CPU ARCHITECTURE3.2.2 Gen
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CHAPTER 3 CPU ARCHITECTURETable 3-3
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CHAPTER 3 CPU ARCHITECTURE3.3 Instr
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CHAPTER 3 CPU ARCHITECTURE3.3.3 Tab
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CHAPTER 3 CPU ARCHITECTURE3.4.2 Sho
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CHAPTER 3 CPU ARCHITECTURE3.4.4 Reg
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CHAPTER 3 CPU ARCHITECTURE3.4.6 Bas
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CHAPTER 4 PORT FUNCTIONSTable 4-1.
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CHAPTER 4 PORT FUNCTIONS4.2.2 Port
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CHAPTER 4 PORT FUNCTIONSFigure 4-5.
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CHAPTER 4 PORT FUNCTIONSFigure 4-7.
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CHAPTER 4 PORT FUNCTIONS4.3 Port Fu
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CHAPTER 4 PORT FUNCTIONS(3) Pull-up
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CHAPTER 5 CLOCK GENERATOR5.1 Clock
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CHAPTER 5 CLOCK GENERATOR5.4 System
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CHAPTER 5 CLOCK GENERATORFigure 5-4
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CHAPTER 5 CLOCK GENERATOR5.6 Changi
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Figure 6-1. Block Diagram of 16-Bit
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CHAPTER 6 16-BIT TIMER 906.3 Contro
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CHAPTER 6 16-BIT TIMER 90(2) Buzzer
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CHAPTER 6 16-BIT TIMER 906.4 Operat
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CHAPTER 6 16-BIT TIMER 906.4.2 Oper
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CHAPTER 6 16-BIT TIMER 906.4.4 16-b
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CHAPTER 6 16-BIT TIMER 906.5 Notes
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER
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CHAPTER 16 ELECTRICAL SPECIFICATION
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CHAPTER 18 RECOMMENDED SOLDERING CO
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APPENDIX A DEVELOPMENT TOOLSThe fol
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APPENDIX A DEVELOPMENT TOOLSA.1 Sof
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APPENDIX A DEVELOPMENT TOOLSA.4 Fla
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APPENDIX B NOTES ON TARGET SYSTEM D
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APPENDIX C REGISTER INDEXC.1 Regist
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APPENDIX C REGISTER INDEXC.2 Regist
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APPENDIX D REVISION HISTORYThe foll
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uPD789074 Subseries 8-Bit Single-Chip Microcontrollers UD - Home

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