uPD789074 Subseries 8-Bit Single-Chip Microcontrollers UD - Home

CHAPTER 3 CPU ARCHITECTURE3.2.3 Special function registers (SFRs)Unlike the general-purpose registers, each special function register has a special function.The special function registers are allocated to the 256-byte area FF00H to FFFFH.The special function registers can be manipulated, like the general-purpose registers, with operation, transfer, andbit manipulation instructions. Manipulatable bit units (1, 8, and 16) differ depending on the special function registertype.Each manipulation bit unit can be specified as follows.• 1-bit manipulationDescribe a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). Thismanipulation can also be specified with an address.• 8-bit manipulationDescribe a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). Thismanipulation can also be specified with an address.• 16-bit manipulationDescribe a symbol reserved by the assembler for the 16-bit manipulation instruction operand. When specifyingan address, describe an even address.Table 3-3 lists the special function registers. The meanings of the symbols in this table are as follows.• SymbolIndicates the addresses of the implemented special function registers. The symbols shown in this column arereserved words in the assembler, and have already been defined in a header file called "sfrbit.h" in the Ccompiler. Therefore, these symbols can be used as instruction operands if an assembler or integrateddebugger is used.• R/WIndicates whether the special function register can be read or written.R/W: Read/writeR: Read onlyW: Write only• Number of bits manipulated simultaneouslyIndicates the bit units (1, 8, and 16) in which the special function register can be manipulated.• After resetIndicates the status of the special function register when the RESET signal is input.50User’s Manual U14801EJ3V1UD