Jens Janssen Diploma Thesis - Prof. Dr. Norbert Wermes ...

More documents

Recommendations

Info

Figure 3.3: The ATLAS hybrid pixel module. The module readout electronicsis mounted on a polyimide printed circuit board (flex-hybrid). The flex-hybridis attached with an adhesive to the bare module (sensor bump bonded to 16FE-I3 chips). The flex-hybrid also provides high-voltage and low-voltage to theattached components. The sensor is wire bonded through a hole in the flexhybridexposing the sensor backplane (p-side). Wire bonds are also used toelectrically interconnect the FE-I3 readout chip to the flex-hybrid.of irradiated sensor material (see section 3.4.2). The use of lightweight materialsis crucial to reduce multiple scattering. The contribution of the pixel detectorto the total inner detector material budged is of the order of 10% X 0 (radiationlength) and 0.05% ⁄ (interaction length) at ÷ =0[6].There are two types of local support structures: staves and sectors. A staveholds 13 pixel modules while a sector holds eight pixel modules. Each barrellayer consists of di erent numbers of staves (22 staves for the b-layer, 38 forthe second and 52 for the third layer) and each end-cap disc is made of eightsectors. This leads to a total number of 1744 pixel modules for the entire pixeldetector.3.3 FE-I3 Pixel Readout ChipThe ATLAS FE-I3 pixel readout chip is implemented in a 0.25 µm CMOS fabricationprocess. The die has a size of 5.4mm◊ 11 mm. 3.5 million transistorsare fabricated on silicon using radiation tolerant design rules 2 to withstand the2 On transistor level: the NMOS transistors are separated by p + guard rings. Also a deepsub-micron technology is beneficial for radiation hardening. Due to the small MOS gate oxidethickness the upcharge is reduced significantly. On design level: single event upset (SEU)tolerant redundant structures/blocks/registers and parity checking. For more information see14
(a) (b)Figure 3.4: On top view of the FE-I3 readout chip. (a) Overview of the mostimportant logic blocks of the FE-I3. (b) Size of the readout chip compared to amatch. Clearly visible are the double column structure and the chip peripheryat the bottom containing the readout logic and bu ers.15
Page 1: Universität BonnPhysikalisches Ins
Page 7 and 8: Chapter 1IntroductionThe ATLAS expe
Page 9 and 10: Chapter 2The LHC Experiment2.1 The
Page 11 and 12: Figure 2.3: Cut-away view of the in
Page 13 and 14: The electromagnetic calorimeter use
Page 15 and 16: Chapter 3Silicon Pixel Detectors3.1
Page 17: Figure 3.2: Layout and interconnect
Page 21: Figure 3.5: The analog pixel block
Page 24 and 25: Figure 3.8: The digital block of th
Page 26 and 27: the digital readout of the chip can
Page 28 and 29: Stopping power [MeV cm 2 /g]100101L
Page 30 and 31: The free charge carriers need to be
Page 32 and 33: The first point particularly concer
Page 34 and 35: Figure 3.14: A 3D n-in-p sensor (le
Page 36 and 37: few µm compared to a few 100 µm).
Page 38 and 39: Figure 4.1: The USBpix test system
Page 40 and 41: e accessed through a 20-bit wide ad
Page 42 and 43: hardware, USBpixdll library uses fu
Page 44 and 45: 100Scan overlaythreshold80604020MSC
Page 46 and 47: mand clock (CCK, 4 MHz 17 ) by mult
Page 48 and 49: aw data word bit [31:0]hit wordw/o
Page 50 and 51: Figure 4.7: Overview of interconnec
Page 52 and 53: SOURCE_SCAN.Module "test"Cluster To
Page 54 and 55: Figure 5.1: The USBpix test setup:
Page 56 and 57: Not only the wafer processing a ect
Page 58 and 59: 2. The tuning was changed to a gain
Page 60 and 61: FDAC The FDAC is a 3-bit pixel regi
Page 62 and 63: probability of 50%. Mathematically,
Page 64 and 65: that the particles first impinge th
Page 66 and 67: 2. Conversion of (clustered) Time-o
Page 68 and 69:
from the expected charge of 10000 e
Page 70 and 71:
6.2 Unirradiated Planar SensorsThe
Page 72 and 73:
Sensor 3631-303 “ATLAS W11 19GR-2
Page 74 and 75:
(a)(b)(c)Figure 6.4: Planar devices
Page 76 and 77:
6.3.1 Results of the Bias ScanLeaka
Page 78 and 79:
(a)(b)Figure 6.7: Leakage current o
Page 80 and 81:
(a)(b)Figure 6.9: FBK 3D devices: m
Page 82 and 83:
Appendix AFE-I3 StandardConfigurati
Page 84 and 85:
Appendix BFPGA ConfigurationRegiste
Page 86 and 87:
Appendix CTuning ResultsThis page i
Page 88 and 89:
Figure C.1: Tuning of the 3631-303
Page 90 and 91:
8642Figure C.3: Tuning of the WR13
Page 92 and 93:
8642Figure C.5: Tuning of the 4EM9
Page 94 and 95:
[13] Peric, I. et al.: The FEI3 rea
Page 96 and 97:
[37] Backhaus, M. et al.: Developme
show all

Jens Janssen Diploma Thesis - Prof. Dr. Norbert Wermes ...

Create successful ePaper yourself

Delete template?

Save as template?