Jens Janssen Diploma Thesis - Prof. Dr. Norbert Wermes ...

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Figure 4.1: The USBpix test system (from left to right): the S3Multi-IO-Board,the Single Module Adapter Card (SMAC), and the Single Chip Card (SCC).upgrades. Besides that, the USBpix test system has to provide most of the functionalityas its predecessor TurboDAQ. The functionality of USBpix includes thefollowing scan types (to name the most important ones):Analog Test Test of the analog pixel blockCrosstalk Scan Measurement of the electronic crosstalk between adjacent pixelsDigital Test Test of the digital pixel block and digital readout chainMonleak Scan Measurement of the leakage currentSource Scan Data taking with radioactive source and external triggerThreshold Scan Measurement of the S-curveGDAC and TDAC Tuning Coarse and fine tuning of the thresholdFDAC Tuning Tuning of the Time-over-Threshold (ToT)ToT Calibration Measurement of the relationship between collected chargeand ToTAdditionally, the integration of the USBpix test system into the framework ofthe EUDET beam telescope is one of the major tasks.4.3 Hardware Parts of USBpixThe USBpix hardware is built up in a modular way (see figure 4.1). It consistsof three di erent PCB boards which are connected over flat ribbon cable and34
(a)Figure 4.2: (a) Block diagram of the S3Multi-IO-Board.S3Multi-IO-Board [35].(b)(b) Picture of theon-board connectors. The entire hardware of the test system is connected via aUSB 2.0 Hi-Speed interface (480 Mbps raw data speed) to a host computer (orDAQ computer) which is running the control software (STcontrol).4.3.1 S3Multi-IO-BoardThe S3Multi-IO-Board is a multi-purpose I/O board (Rev. 1.03, see figure 4.2).It is the central control unit of the test system containing all of the programmablehardware parts. The communication between the host computerand the S3Multi-IO-Board is implemented in an 8051-based USB-capable microcontroller(Cypress CY7C68013A). The 8051-microcontroller steers the communicationbetween hardware parts on the S3Multi-IO-Board (FPGA, EEPROM,programmable clock generator, ADC; for more details see following sections)and the software running on the host computer. To set the programmable clockgenerator (Cypress CY22150FZXI) or to read out the analog-to-digital converters(Maxim MAX1238, located on the Adapter Card) the microcontrolleruses a 2-wire I C serial interface. The EEPROM (Microchip 24LC128), whichcontains the firmware of the microcontroller, is serially connected to the 8051-microcontroller. Registers and Block RAM inside the FPGA (Xilinx Spartan-3XC3S1000-FGG320) can be accessed by using the Slow Interface. The SlowInterface 3 is a 8-bit wide parallel data bus with a 48 MHz clock (UCLK, internalclock of the microcontroller). The address space is 16-bit wide. Themicrocontroller and the FPGA have access to 16 Mbit asynchronous SRAM.The SRAM (Cypress CY7C1061AV33) is connected to a 16-bit wide data bus 4 .The clock speed depends on whether the microcontroller or the FPGA is accessingthe SRAM and is 48 MHz or 40 MHz, respectively. The memory can3 The name derives from the fact that the internal clock was initially running on 24 MHz.The speed of the internal clock was changed during this thesis.4 A16-bitwideparallelinterfaceisavailableinhardwarebutnotimplementedinsoftware.Currently, only a 8-bit wide data bus is used.35
Page 1: Universität BonnPhysikalisches Ins
Page 7 and 8: Chapter 1IntroductionThe ATLAS expe
Page 9 and 10: Chapter 2The LHC Experiment2.1 The
Page 11 and 12: Figure 2.3: Cut-away view of the in
Page 13 and 14: The electromagnetic calorimeter use
Page 15 and 16: Chapter 3Silicon Pixel Detectors3.1
Page 17 and 18: Figure 3.2: Layout and interconnect
Page 19 and 20: (a) (b)Figure 3.4: On top view of t
Page 21: Figure 3.5: The analog pixel block
Page 24 and 25: Figure 3.8: The digital block of th
Page 26 and 27: the digital readout of the chip can
Page 28 and 29: Stopping power [MeV cm 2 /g]100101L
Page 30 and 31: The free charge carriers need to be
Page 32 and 33: The first point particularly concer
Page 34 and 35: Figure 3.14: A 3D n-in-p sensor (le
Page 36 and 37: few µm compared to a few 100 µm).
Page 40 and 41: e accessed through a 20-bit wide ad
Page 42 and 43: hardware, USBpixdll library uses fu
Page 44 and 45: 100Scan overlaythreshold80604020MSC
Page 46 and 47: mand clock (CCK, 4 MHz 17 ) by mult
Page 48 and 49: aw data word bit [31:0]hit wordw/o
Page 50 and 51: Figure 4.7: Overview of interconnec
Page 52 and 53: SOURCE_SCAN.Module "test"Cluster To
Page 54 and 55: Figure 5.1: The USBpix test setup:
Page 56 and 57: Not only the wafer processing a ect
Page 58 and 59: 2. The tuning was changed to a gain
Page 60 and 61: FDAC The FDAC is a 3-bit pixel regi
Page 62 and 63: probability of 50%. Mathematically,
Page 64 and 65: that the particles first impinge th
Page 66 and 67: 2. Conversion of (clustered) Time-o
Page 68 and 69: from the expected charge of 10000 e
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Page 72 and 73: Sensor 3631-303 “ATLAS W11 19GR-2
Page 74 and 75: (a)(b)(c)Figure 6.4: Planar devices
Page 76 and 77: 6.3.1 Results of the Bias ScanLeaka
Page 78 and 79: (a)(b)Figure 6.7: Leakage current o
Page 80 and 81: (a)(b)Figure 6.9: FBK 3D devices: m
Page 82 and 83: Appendix AFE-I3 StandardConfigurati
Page 84 and 85: Appendix BFPGA ConfigurationRegiste
Page 86 and 87: Appendix CTuning ResultsThis page i
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Figure C.1: Tuning of the 3631-303
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8642Figure C.3: Tuning of the WR13
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8642Figure C.5: Tuning of the 4EM9
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[13] Peric, I. et al.: The FEI3 rea
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[37] Backhaus, M. et al.: Developme
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Jens Janssen Diploma Thesis - Prof. Dr. Norbert Wermes ...

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