Jens Janssen Diploma Thesis - Prof. Dr. Norbert Wermes ...

equired radiation tolerance up to a total dose of 50 Mrad. The chip contains2880 readout channels arranged in matrix of 160 rows ◊ 18 columns. The sizeof each readout cell is 50 µm ◊ 400 µm (row-to-row pitch ◊ column-to-columnpitch). The power consumption should be less than 40 µW per readout channelto fulfill the design requirements [11]. However, the chip typically draws 40 mAof current from a 2V (digital supply voltage) supply and 80 mA of current froma 1.6V (analog supply voltage) supply (see also [12]), which is 30 µW abovedesign requirements per readout channel.Figure 3.4 shows the most important logic blocks of the FE-I3. Each pixelconsists of an analog and a digital block. The task of the analog pixel blockis to amplify and shape the input signal charge which is generated by particleshitting the sensor. The digital block comprises all digital elements beginningfrom the digital pixel block and ending at the readout controller in the chipperiphery. The digital pixel block communicates with the logic located in thechip periphery and transmits the hit data. The 18 pixel columns are alignedto 9 double columns. The double column comprises 320 readout channels, eachsharing the same column bus, column arbitration unit (CAU, also referred to ascolumn readout controller) and end-of-column (EoC) bu er. Beside the doublecolumn readout logic (CAU and EoC bu er), also the chip level readout controller(ROC) is located in the chip periphery. The ROC collects the hit dataand sends them out serially. The following sections will give a more detaileddescription about the analog and digital design.3.3.1 Chip ConfigurationThe FE-I3 readout chip has a 14-bit local configuration register which is locatedin each of the 2880 pixel readout blocks. Also 231-bit long global configurationregister exists. Parts of the global configuration register are located underneaththe pixel matrix and in the chip periphery in vicinity of the corresponding logicblocks. All configuration bits are stored in single event upset (SEU) tolerantlatches/RAM cells.The latches can be accessed by using two long shift register. One 231-bitlong shit register for the global register and one 2880-bit long shift register foraccessing the pixel register bits.An additional 29-bit long command register controls the shifting of the bitpattern and the latching of the bits into the corresponding RAM cells. Thecommand register determines into which shift register the received bit patternis shifted. It also determines into which local register the pixel shift register islatched.Three input signals are needed: command clock (CCK), data input (DI)and a load signal (LD). The clock is sent in parallel with data: DI must besynchronous to the CCK and the CCK is enabled only during shifting the data.The procedure is as follows: first, the 29-bit command has to be written tothe command register to get access the intended configuration register (clockcommand). When LD is low the command data can be shifted into the commandregister (CCK enabled for 29 clock cycles). To latch the command data, LDmust be asserted. Immediately, the command becomes active. Second, theconfiguration data is shifted to the shift register. The LD stays asserted and[8, 9, 10, 11].16