Jens Janssen Diploma Thesis - Prof. Dr. Norbert Wermes ...

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Appendix AFE-I3 StandardConfigurationName ValueTDAC 64FDAC 4ENHITBUS oMASK oKILL oSELECT oFigure A.1: FE-I3 standard pixel configuration.78
Name Value Name ValueLATENCY 255 ENABLECOL6 1SELFTRGDELAY 0 TESTDACITRIMTH 0SELFTRGWIDTH 0 ITRIMTHDAC 64ENABLESELFTRG 0 IFDAC 32ENABLEHITPARITY 0 TESTDACIF 0SELECTDO 8 ENABLECOL5 1SELECTMONHIT 1 TESTDACITRIMIF 0TSITSCENABLE 1 ITRIMIFDAC 16SELECTDATAPHASE 0 VCALDAC 0ENABLEEOEPARITY 0 TESTDACVCAL 1HITBUSSCALER 0 ENABLECOL4 0MONLEAKADC 0 HITINJECTCAPSEL 0AREGTRIM 0 ENABLEEXTINJ 0ENABLEAREGMEAS 0 TESTANALOGREF 0AREGMEAS 0 EOCMUXCONTROL 0ENABLEAREG 0 CEUCLOCKCONTROL 3ENABLELVDSREFMEAS 0 ENABLEDIGITALINJ 0DREGTRIM 0 ENABLECOL3 1ENABLEDREGMEAS 0 TESTDACITH1 0DREGMEAS 0 ITH1DAC 0CAPMEASCIRCUIT 0 ITH2DAC 0ENABLECAPTEST 0 TESTDACITH2 0ENABLEANALOGOUT 0 ENABLECOL2 1TESTPIXELMUX 2 TESTDACIL 0ENABLEVCALMEAS 0 ILDAC 64ENABLELEAKMEAS 0 IL2DAC 64ENABLEBUFFERBOOST 0 TESTDACIL2 0ENABLECOL8 1 ENABLECOL1 1TESTDACIVDD2 0 THRMIN 0IVDD2DAC 64 THRDUB 0IDDAC 64 READMODE 0TESTDACID 0 ENABLECOL0 1ENABLECOL7 1 HITBUSENABLE 1TESTDACIP2 0 GLOBALTDAC 14IP2DAC 64 ENABLETUNE 0IPDAC 64 ENABLEBIASCOMP 1TESTDACIP 0 ENABLEIPMONITOR 0Table A.1: FE-I3 standard global configuration.79
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Universität BonnPhysikalisches Ins
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Chapter 1IntroductionThe ATLAS expe
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Chapter 2The LHC Experiment2.1 The
Page 11 and 12:
Figure 2.3: Cut-away view of the in
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The electromagnetic calorimeter use
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Chapter 3Silicon Pixel Detectors3.1
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Figure 3.2: Layout and interconnect
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(a) (b)Figure 3.4: On top view of t
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Figure 3.5: The analog pixel block
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Figure 3.8: The digital block of th
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the digital readout of the chip can
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Stopping power [MeV cm 2 /g]100101L
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The free charge carriers need to be
Page 32 and 33: The first point particularly concer
Page 34 and 35: Figure 3.14: A 3D n-in-p sensor (le
Page 36 and 37: few µm compared to a few 100 µm).
Page 38 and 39: Figure 4.1: The USBpix test system
Page 40 and 41: e accessed through a 20-bit wide ad
Page 42 and 43: hardware, USBpixdll library uses fu
Page 44 and 45: 100Scan overlaythreshold80604020MSC
Page 46 and 47: mand clock (CCK, 4 MHz 17 ) by mult
Page 48 and 49: aw data word bit [31:0]hit wordw/o
Page 50 and 51: Figure 4.7: Overview of interconnec
Page 52 and 53: SOURCE_SCAN.Module "test"Cluster To
Page 54 and 55: Figure 5.1: The USBpix test setup:
Page 56 and 57: Not only the wafer processing a ect
Page 58 and 59: 2. The tuning was changed to a gain
Page 60 and 61: FDAC The FDAC is a 3-bit pixel regi
Page 62 and 63: probability of 50%. Mathematically,
Page 64 and 65: that the particles first impinge th
Page 66 and 67: 2. Conversion of (clustered) Time-o
Page 68 and 69: from the expected charge of 10000 e
Page 70 and 71: 6.2 Unirradiated Planar SensorsThe
Page 72 and 73: Sensor 3631-303 “ATLAS W11 19GR-2
Page 74 and 75: (a)(b)(c)Figure 6.4: Planar devices
Page 76 and 77: 6.3.1 Results of the Bias ScanLeaka
Page 78 and 79: (a)(b)Figure 6.7: Leakage current o
Page 80 and 81: (a)(b)Figure 6.9: FBK 3D devices: m
Page 84 and 85: Appendix BFPGA ConfigurationRegiste
Page 86 and 87: Appendix CTuning ResultsThis page i
Page 88 and 89: Figure C.1: Tuning of the 3631-303
Page 90 and 91: 8642Figure C.3: Tuning of the WR13
Page 92 and 93: 8642Figure C.5: Tuning of the 4EM9
Page 94 and 95: [13] Peric, I. et al.: The FEI3 rea
Page 96 and 97: [37] Backhaus, M. et al.: Developme
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