Jens Janssen Diploma Thesis - Prof. Dr. Norbert Wermes ...

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100Scan overlaythreshold80604020MSC0714B - untuned TPLL/TPCCMSC0714B - untuned USBpix02000 3000 4000 5000 6000Threshold (e)(a)(b)Scan overlaynoiseMSC0714B - untuned TPLL/TPCCMSC0714B - untuned USBpix15010050060 80 100 120Noise (e)(c)Figure 4.3: Comparison between USBpix and TurboDAQ (in the figures referredto as TPLL/TPCC) [37]. The FE-I3 readout chip (7-14B) was not connectedto a sensor (measured noise of approximately 90 electrons). It was left untunedto not bias the results by using di erent tuning algorithms on each readoutsystem. Instead, the standard configuration was used (see [34]). (a) Overlay plotof the threshold distribution. (b) Pixel-by-pixel comparison of the threshold.(c) Overlay plot of the noise distribution.40
Figure 4.4: USBpix HDL design.top-level module. All I/O ports of the top-level module are expected to be realizedin hardware (I/O ports of the FPGA) as described in the user constraintsfile (UCF). All remaining modules communicate with other modules througha set of I/O ports. Internally, every module uses sequential and combinatoriallogic which is connected to I/O ports, internal wires or internal registers.The functionality of every module is as follows: the top-level module is calledUSBpix.v. Every I/O port of USBpix.v is assigned to an I/O pin on the FPGAchip as described in the user constraints file USBpix_S3MultiIO_V103.ucf. Internally,USBpix.v is connected to instances of other modules which form asub-hierarchy. Every logic element, which is instantiated by synthesis tool 14 ,belongs to a clock domain. A clock domain determines the signal frequency 15of a section of logic. Inside this section all synchronous logic (e.g. flip-flops) isclocked by the same net (e.g. clock net with a clock of a certain frequency andphase). The clock domain also determines the length of signal paths betweenlogic elements to satisfy constraints as defined in the UCF file. The calculationof signal path is integral part of the process of placing and routing 16 .The FPGA receives the FCLK (see section 4.5) from the microcontroller.The digital clock manager (DCM), which is instantiated inside the moduleclock_generator.v, generates the crossing clock (XCK, 40 MHz) and com-14 Synthesis is a process by which an abstract form of desired circuit behavior (e.g. as definedby HDL) is turned into a design implementation in terms of logic elements (e.g netlist).15 All signals in a clock domain are synchronized to a fixed clock. Signals which are crossingfrom one clock domain into another have to be synchronized. Even input signals of the FPGAwhich have the same frequency must be synchronized (phase alignment). To avoid metastableevents, two stage synchronizer are used to synchronize all input signals into the FPGA.16 Place and route (P&R) describes a processes where the netlist is mapped to the FPGAphysical resources.41
Page 1: Universität BonnPhysikalisches Ins
Page 7 and 8: Chapter 1IntroductionThe ATLAS expe
Page 9 and 10: Chapter 2The LHC Experiment2.1 The
Page 11 and 12: Figure 2.3: Cut-away view of the in
Page 13 and 14: The electromagnetic calorimeter use
Page 15 and 16: Chapter 3Silicon Pixel Detectors3.1
Page 17 and 18: Figure 3.2: Layout and interconnect
Page 19 and 20: (a) (b)Figure 3.4: On top view of t
Page 21: Figure 3.5: The analog pixel block
Page 24 and 25: Figure 3.8: The digital block of th
Page 26 and 27: the digital readout of the chip can
Page 28 and 29: Stopping power [MeV cm 2 /g]100101L
Page 30 and 31: The free charge carriers need to be
Page 32 and 33: The first point particularly concer
Page 34 and 35: Figure 3.14: A 3D n-in-p sensor (le
Page 36 and 37: few µm compared to a few 100 µm).
Page 38 and 39: Figure 4.1: The USBpix test system
Page 40 and 41: e accessed through a 20-bit wide ad
Page 42 and 43: hardware, USBpixdll library uses fu
Page 46 and 47: mand clock (CCK, 4 MHz 17 ) by mult
Page 48 and 49: aw data word bit [31:0]hit wordw/o
Page 50 and 51: Figure 4.7: Overview of interconnec
Page 52 and 53: SOURCE_SCAN.Module "test"Cluster To
Page 54 and 55: Figure 5.1: The USBpix test setup:
Page 56 and 57: Not only the wafer processing a ect
Page 58 and 59: 2. The tuning was changed to a gain
Page 60 and 61: FDAC The FDAC is a 3-bit pixel regi
Page 62 and 63: probability of 50%. Mathematically,
Page 64 and 65: that the particles first impinge th
Page 66 and 67: 2. Conversion of (clustered) Time-o
Page 68 and 69: from the expected charge of 10000 e
Page 70 and 71: 6.2 Unirradiated Planar SensorsThe
Page 72 and 73: Sensor 3631-303 “ATLAS W11 19GR-2
Page 74 and 75: (a)(b)(c)Figure 6.4: Planar devices
Page 76 and 77: 6.3.1 Results of the Bias ScanLeaka
Page 78 and 79: (a)(b)Figure 6.7: Leakage current o
Page 80 and 81: (a)(b)Figure 6.9: FBK 3D devices: m
Page 82 and 83: Appendix AFE-I3 StandardConfigurati
Page 84 and 85: Appendix BFPGA ConfigurationRegiste
Page 86 and 87: Appendix CTuning ResultsThis page i
Page 88 and 89: Figure C.1: Tuning of the 3631-303
Page 90 and 91: 8642Figure C.3: Tuning of the WR13
Page 92 and 93: 8642Figure C.5: Tuning of the 4EM9
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[13] Peric, I. et al.: The FEI3 rea
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[37] Backhaus, M. et al.: Developme
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Jens Janssen Diploma Thesis - Prof. Dr. Norbert Wermes ...

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