Jens Janssen Diploma Thesis - Prof. Dr. Norbert Wermes ...

More documents

Recommendations

Info

Appendix BFPGA ConfigurationRegisters for SourceScan/EUDETCS_READOUT_MODE 2-bit register. 2’b11: source scan mode.CS_TRIGGER_MODE 2-bit register. 2’b01: no-handshake mode; 2’b10: simplehandshake mode; 2’b11: trigger data handshake mode.CS_COUNTER_MODE 2-bit register. 2’b00: triggers; 2’b01: hit words; 2’b10: EoEwords.CS_NUMBER_OF_EVENTS 32-bit register. Set up the maximum number of events(triggers, hit words or EoE words). After the desired number of events isreached, the measurement stops automatically.CS_MEASUREMENT_START_STOP 1-bit register. If asserted, the measurement starts.If de-asserted, the measurement stops.CS_MEASUREMENT_PAUSE_RESUME 1-bit register. If asserted, the measurementstops without resetting the counters. If de-asserted, the measurementcontinues.CS_ENABLE_RJ45 1-bit register. If enabled, the RJ45 port must be used toconnect the S3Multi-IO-Board to the TLU.CS_XCK_PHASE 1-bit register. If enabled, the XCK phase is shifted by 180°.CS_DISABLE_EOE_WORD_COUNTER 1-bit register. If enabled, directly accept newtrigger after all EoE words arrived. If disabled, wait for data as inCS_LENGTH_TOTAL specified.CS_LENGTH_TOTAL 16-bit register. Maximum waiting time (in units of bunchcrossings) to receive all data words from the FE-I3 readout chip thatbelongs to a trigger. If the timeout is reached, EoE/hit word timeout isasserted (see figure 4.1). 0 means disabled (standard).80
CS_EOE_HIT_WORD_TIME_OUT 8-bit register. Timeout (in units of bunch crossings)for for receiving data words (hit/EoE word) from the FE-I3 readoutchip. If the timeout is reached, BCID window timeout is asserted (seefigure 4.1). 0 means disabled (standard).CS_SAVE_UNKNOWN_WORD 1-bit register. If disabled, data received from FE-I3readout chip that is no hit word or EoE is ignored (standard). If enabled,all data gets saved.CS_MINIMUM_TRIGGER_LENGTH 8-bit register. Set up the minimum length (inunits of bunch crossings) of the trigger signal to be accepted. If set to 0every trigger is accepted (standard).CS_SAVE_COMPLETE_TRIGGER_NUMBER 1-bit register. If disabled, trigger wordwith status data is saved (standard). If enabled, the full trigger word getssaved (see figure 4.1).CS_TLU_TRIGGER_DATA_LENGTH 8-bit register. Set up the length of the triggernumber in bits (standard value is 32).CS_TLU_TRIGGER_DATA_DELAY 8-bit register. Set up additional delay to thetrigger data shift register (standard value is 0).CS_TLU_TRIGGER_DATA_MSB_FIRST 1-bit register. If disabled, the LSB is clockedfirst (standard). If enabled, the MSB is clocked first.CS_TLU_TRIGGER_LOW_TIME_OUT 8-bit register. Timeout for the trigger signalto be de-asserted. If the timeout is reached, the source scan will bestopped. 0 means disabled (standard).81
Page 1:
Universität BonnPhysikalisches Ins
Page 7 and 8:
Chapter 1IntroductionThe ATLAS expe
Page 9 and 10:
Chapter 2The LHC Experiment2.1 The
Page 11 and 12:
Figure 2.3: Cut-away view of the in
Page 13 and 14:
The electromagnetic calorimeter use
Page 15 and 16:
Chapter 3Silicon Pixel Detectors3.1
Page 17 and 18:
Figure 3.2: Layout and interconnect
Page 19 and 20:
(a) (b)Figure 3.4: On top view of t
Page 21:
Figure 3.5: The analog pixel block
Page 24 and 25:
Figure 3.8: The digital block of th
Page 26 and 27:
the digital readout of the chip can
Page 28 and 29:
Stopping power [MeV cm 2 /g]100101L
Page 30 and 31:
The free charge carriers need to be
Page 32 and 33:
The first point particularly concer
Page 34 and 35: Figure 3.14: A 3D n-in-p sensor (le
Page 36 and 37: few µm compared to a few 100 µm).
Page 38 and 39: Figure 4.1: The USBpix test system
Page 40 and 41: e accessed through a 20-bit wide ad
Page 42 and 43: hardware, USBpixdll library uses fu
Page 44 and 45: 100Scan overlaythreshold80604020MSC
Page 46 and 47: mand clock (CCK, 4 MHz 17 ) by mult
Page 48 and 49: aw data word bit [31:0]hit wordw/o
Page 50 and 51: Figure 4.7: Overview of interconnec
Page 52 and 53: SOURCE_SCAN.Module "test"Cluster To
Page 54 and 55: Figure 5.1: The USBpix test setup:
Page 56 and 57: Not only the wafer processing a ect
Page 58 and 59: 2. The tuning was changed to a gain
Page 60 and 61: FDAC The FDAC is a 3-bit pixel regi
Page 62 and 63: probability of 50%. Mathematically,
Page 64 and 65: that the particles first impinge th
Page 66 and 67: 2. Conversion of (clustered) Time-o
Page 68 and 69: from the expected charge of 10000 e
Page 70 and 71: 6.2 Unirradiated Planar SensorsThe
Page 72 and 73: Sensor 3631-303 “ATLAS W11 19GR-2
Page 74 and 75: (a)(b)(c)Figure 6.4: Planar devices
Page 76 and 77: 6.3.1 Results of the Bias ScanLeaka
Page 78 and 79: (a)(b)Figure 6.7: Leakage current o
Page 80 and 81: (a)(b)Figure 6.9: FBK 3D devices: m
Page 82 and 83: Appendix AFE-I3 StandardConfigurati
Page 86 and 87: Appendix CTuning ResultsThis page i
Page 88 and 89: Figure C.1: Tuning of the 3631-303
Page 90 and 91: 8642Figure C.3: Tuning of the WR13
Page 92 and 93: 8642Figure C.5: Tuning of the 4EM9
Page 94 and 95: [13] Peric, I. et al.: The FEI3 rea
Page 96 and 97: [37] Backhaus, M. et al.: Developme
show all

Jens Janssen Diploma Thesis - Prof. Dr. Norbert Wermes ...

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?