ADV7174/ADV7179 Chip Scale PAL/NTSC Video ... - Analog Devices

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ADV7174/ADV7179 Mode 2: Slave Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = X X X X X 1 0 0) In this mode, the ADV7174/ADV7179 accepts horizontal and vertical SYNC signals. A coincident low transition of both and VSYNC inputs indicates the start of an odd field. A VSYNC low HSYNC BLANK VSYNC HSYNC BLANK VSYNC Rev. B | Page 22 of 52 transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7174/ADV7179 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL). DISPLAY DISPLAY VERTICAL BLANK 522 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 HSYNC BLANK VSYNC HSYNC BLANK VSYNC EVEN FIELD ODD FIELD DISPLAY DISPLAY VERTICAL BLANK 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 DISPLAY ODD FIELD EVEN FIELD Figure 27. Timing Mode 2 (NTSC) 622 623 624 625 1 2 3 4 5 6 7 21 22 23 DISPLAY EVEN FIELD VERTICAL BLANK ODD FIELD VERTICAL BLANK DISPLAY 309 310 311 312 313 314 315 316 317 318 319 320 334 335 336 ODD FIELD EVEN FIELD Figure 28. Timing Mode 2 (PAL) DISPLAY 02980-A-028 02980-A-027
Mode 2: Master Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = X X X X X 1 0 1) In this mode, the ADV7174/ADV7179 can generate horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the HSYNC VSYNC BLANK PIXEL DATA HSYNC VSYNC BLANK PIXEL DATA PAL = 12 × CLOCK/2 NTSC = 16 × CLOCK/2 Rev. B | Page 23 of 52 ADV7174/ADV7179 BLANK input is disabled, the ADV7174/ADV7179 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL). Figure 29 illustrates the HSYNC, BLANK, and VSYNC for an even-toodd field transition relative to the pixel data. Figure 30 illustrates the HSYNC, BLANK, and VSYNC for an odd-toeven field transition relative to the pixel data. Cb Y Cr Y PAL = 132 × CLOCK/2 NTSC = 122 × CLOCK/2 02980-A-029 Figure 29. Timing Mode 2 Even-to-Odd Field Transition Master/Slave PAL = 12 × CLOCK/2 NTSC = 16 × CLOCK/2 PAL = 132 × CLOCK/2 NTSC = 122 × CLOCK/2 PAL = 864 × CLOCK/2 NTSC = 858 × CLOCK/2 Cb Y Cr Y Cb Figure 30. Timing Mode 2 Odd-to-Even Field Transition Master/Slave 02980-A-082
Page 1 and 2: FEATURES ITU-R1 BT601/BT656 YCrCb t
Page 3 and 4: Appendix 3—Copy Generation Manage
Page 5 and 6: 2.8 V TIMING SPECIFICATIONS VAA = 2
Page 7 and 8: 3.3 V TIMING SPECIFICATIONS VAA = 3
Page 9 and 10: ABSOLUTE MAXIMUM RATINGS Table 5. P
Page 11 and 12: GENERAL DESCRIPTION The ADV7174/ADV
Page 13 and 14: TYPICAL PERFORMANCE CHARACTERISTICS
Page 15 and 16: MAGNITUDE (dB) 0 -10 -20 -30 -40 -5
Page 17 and 18: RTC H/LTRANSITION COUNT START 128 C
Page 19 and 20: H V F H V DISPLAY DISPLAY VERTICAL
Page 21: Mode 1: Master Option HSYNC, BLANK,
Page 25 and 26: POWER-ON RESET After power-up, it i
Page 27 and 28: REGISTER PROGRAMMING This section d
Page 29 and 30: MODE REGISTER 1 (MR1) Bits: MR17-MR
Page 31 and 32: MODE REGISTER 3 (MR3) Bits: MR37-MR
Page 33 and 34: TIMING MODE REGISTER 0 (TR0) Bits:
Page 35 and 36: SUBCARRIER FREQUENCY REGISTERS 3-0
Page 37 and 38: TELETEXT REQUEST CONTROL REGISTER (
Page 39 and 40: APPENDIX 1—BOARD DESIGN AND LAYOU
Page 41 and 42: APPENDIX 2—CLOSED CAPTIONING The
Page 43 and 44: APPENDIX 4—WIDE SCREEN SIGNALING
Page 45 and 46: APPENDIX 6—WAVEFORMS NTSC WAVEFOR
Page 47 and 48: PAL WAVEFORMS 989.7mV 1288.6mV 650m
Page 49 and 50: APPENDIX 7—OPTIONAL OUTPUT FILTER
Page 51 and 52: Table 26. PAL-60 (FSC = 4.43361875

ADV7174/ADV7179 Chip Scale PAL/NTSC Video ... - Analog Devices

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