ADV7174/ADV7179 Chip Scale PAL/NTSC Video ... - Analog Devices

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ADV7174/ADV7179 MODE REGISTER 4 (MR4) Bits: MR47–MR40 Address: SR4–SR0 = 04H Mode Register 4 is an 8-bit-wide register. Figure 42 shows the various operations under the control of Mode Register 4. MR47 MR46 MR45 MR44 MR43 MR42 MR47 (0) ZERO SHOULD BE WRITTEN TO THIS BIT SLEEP MODE CONTROL MR46 0 DISABLE 1 ENABLE ACTIVE VIDEO FILTER CONTROL MR45 0 DISABLE 1 ENABLE PEDESTAL CONTROL MR44 0 PEDESTAL OFF 1 PEDESTAL ON VSYNC_3H MR43 0 DISABLE 1 ENABLE Figure 42. Mode Register 4 Rev. B | Page 32 of 52 RGB SYNC MR42 0 DISABLE 1 ENABLE MR41 MR40 RGB/YUV CONTROL MR41 0 RGB OUTPUT 1 YPbPr OUTPUT OUTPUT SELECT MR40 0 YC OUTPUT 1 RGB/YPbPr OUTPUT Table 14. MR4 Bit Description Bit Name Bit No. Description Output Select MR40 This bit specifies if the part is in composite video or RGB/YPbPr mode. RGB/YPbPr Control MR41 This bit enables the output from the RGB DACs to be set to YPbPr output video standard. RGB Sync MR42 This bit is used to set up the RGB outputs with the sync information encoded on all RGB outputs. VSYNC_3H MR43 When this bit is enabled (1) in slave mode, it is possible to drive the VSYNC active low input for 2.5 lines in PAL mode and three lines in NTSC mode. When this bit is enabled in master mode, the ADV7174/ADV7179 outputs an active low VSYNC signal for three lines in NTSC mode and 2.5 lines in PAL mode. Pedestal Control MR44 This bit specifies whether a pedestal is to be generated on the NTSC composite video signal. This bit is invalid if the ADV7174/ ADV7179 is configured in PAL mode. Active Video Filter Control MR45 This bit controls the filter mode applied outside the active video portion of the line. This filter ensures that the sync rise and fall times are always on spec regardless of which luma filter is selected. A Logic 1 enables this mode. Sleep Mode Control MR46 When this bit is set (1), sleep mode is enabled. With this mode enabled, the ADV7174/ADV7179 power consumption is reduced to typically 200 nA. The I 2 C registers can be written to and read from when the ADV7174/ADV7179 is in sleep mode. If MR46 is set to a (0) when the device is in sleep mode, the ADV7174/ADV7179 comes out of sleep mode and resumes normal operation. Also, if the RESET signal is applied during sleep mode, the ADV7174/ADV7179 comes out of sleep mode and resumes normal operation. Reserved MR47 A Logic 0 should be written to this bit. 02980-A-041
TIMING MODE REGISTER 0 (TR0) Bits: TR07–TR00 Address: SR4–SR0 = 07H Rev. B | Page 33 of 52 ADV7174/ADV7179 Figure 43 shows the various operations under the control of Timing Register 0. This register can be read from as well as written to. TR07 TR06 TR05 TR04 TR03 TR02 TIMING REGISTER RESET TR07 PIXEL PORT CONTROL TR06 0 8 BIT 1 FORBIDDEN LUMA DELAY TR05 TR04 0 0 0ns DELAY 0 1 74ns DELAY 1 0 148ns DELAY 1 1 222ns DELAY BLANK INPUT CONTROL TR03 0 ENABLE 1 DISABLE Figure 43. Timing Register 0 TIMING MODE SELECTION TR02 TR01 0 0 MODE 0 0 1 MODE 1 1 0 MODE 2 1 1 MODE 3 TR01 TR00 MASTER/SLAVE CONTROL TR00 0 SLAVE TIMING 1 MASTER TIMING Table 15. TR0 Bit Description Bit Name Bit No. Description Master/Slave Control TR00 This bit controls whether the ADV7174/ADV7179 is in master or slave mode. Timing Mode Selection TR02–TR01 These bits control the timing mode of the ADV7174/ADV7179. These modes are described in more detail in the 3.3 V Timing Specifications table. BLANK Input Control TR03 This bit controls whether the BLANK input is used when the part is in slave mode. Luma Delay TR05–TR04 These bits control the addition of a luminance delay. Each bit represents a delay of 74 ns. Pixel Port Control TR06 This bit is used to set the pixel port to accept 8-bit or YCrCb data on Pins P7–P0. 0 must be written here. Timing Register Reset TR07 Toggling the TR07 from low to high and to low again resets the internal timing counters. This bit should be toggled after power-up, reset, or changing to a new timing mode. 02980-A-042
Page 1 and 2: FEATURES ITU-R1 BT601/BT656 YCrCb t
Page 3 and 4: Appendix 3—Copy Generation Manage
Page 5 and 6: 2.8 V TIMING SPECIFICATIONS VAA = 2
Page 7 and 8: 3.3 V TIMING SPECIFICATIONS VAA = 3
Page 9 and 10: ABSOLUTE MAXIMUM RATINGS Table 5. P
Page 11 and 12: GENERAL DESCRIPTION The ADV7174/ADV
Page 13 and 14: TYPICAL PERFORMANCE CHARACTERISTICS
Page 15 and 16: MAGNITUDE (dB) 0 -10 -20 -30 -40 -5
Page 17 and 18: RTC H/LTRANSITION COUNT START 128 C
Page 19 and 20: H V F H V DISPLAY DISPLAY VERTICAL
Page 21 and 22: Mode 1: Master Option HSYNC, BLANK,
Page 23 and 24: Mode 2: Master Option HSYNC, VSYNC,
Page 25 and 26: POWER-ON RESET After power-up, it i
Page 27 and 28: REGISTER PROGRAMMING This section d
Page 29 and 30: MODE REGISTER 1 (MR1) Bits: MR17-MR
Page 31: MODE REGISTER 3 (MR3) Bits: MR37-MR
Page 35 and 36: SUBCARRIER FREQUENCY REGISTERS 3-0
Page 37 and 38: TELETEXT REQUEST CONTROL REGISTER (
Page 39 and 40: APPENDIX 1—BOARD DESIGN AND LAYOU
Page 41 and 42: APPENDIX 2—CLOSED CAPTIONING The
Page 43 and 44: APPENDIX 4—WIDE SCREEN SIGNALING
Page 45 and 46: APPENDIX 6—WAVEFORMS NTSC WAVEFOR
Page 47 and 48: PAL WAVEFORMS 989.7mV 1288.6mV 650m
Page 49 and 50: APPENDIX 7—OPTIONAL OUTPUT FILTER
Page 51 and 52: Table 26. PAL-60 (FSC = 4.43361875

ADV7174/ADV7179 Chip Scale PAL/NTSC Video ... - Analog Devices

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