ADV7174/ADV7179 Chip Scale PAL/NTSC Video ... - Analog Devices

3.3 V TIMING SPECIFICATIONS
VAA = 3.0 V–3.6 V 1 , VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX 2 , unless otherwise noted.
Rev. B | Page 7 of 52
ADV7174/ADV7179
Table 4.
Parameter Conditions1 3, 4
MPU PORT
Min Typ Max Unit
SCLOCK Frequency 0 400 kHz
SCLOCK High Pulse Width, t1 0.6 μs
SCLOCK Low Pulse Width, t2 1.3 μs
Hold Time (Start Condition), t3 After this period, the first clock is generated 0.6 μs
Setup Time (Start Condition), t4 Relevant for repeated start condition 0.6 μs
Data Setup Time, t5 100 ns
SDATA, SCLOCK Rise Time, t6 300 ns
SDATA, SCLOCK Fall Time, t7 300 ns
Setup Time (Stop Condition), t8
3, 5
ANALOG OUTPUTS
0.6 μs
Analog Output Delay 7 ns
DAC Analog Output Skew
4, 5
CLOCK CONTROL AND PIXEL PORT
0 ns
fCLOCK 27 MHz
Clock High Time, t9 8 ns
Clock Low Time, t10 8 ns
Data Setup Time, t11 3.5 ns
Data Hold Time, t12 4 ns
Control Setup Time, t11 4 ns
Control Hold Time, t12 3 ns
Digital Output Access Time, t13 12 ns
Digital Output Hold Time, t14 8 ns
Pipeline Delay, tPD 6 3, 4
TELETEXT
48 Clock Cycles
Digital Output Access Time, t16 23 ns
Data Setup Time, t17 2 ns
Data Hold Time, t18
RESET CONTROL
6 ns
, 3 4
RESET Low Time 6 ns
1 The maximum/minimum specifications are guaranteed over this range. The maximum/minimum values are typical over 3.0 V to 3.6 V range.
2 Temperature range TMIN to TMAX: –40°C to +85°C.
3 TTL input values are 0 V to 3 V, with input rise/fall times −3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load –10 pF.
4 Guaranteed by characterization.
5 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6 See Figure 60.