SPIRE Design Description - Research Services
SPIRE Design Description - Research Services
SPIRE Design Description - Research Services
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.<br />
FPGA<br />
Sinewave<br />
generation<br />
Reference<br />
0<br />
0<br />
0<br />
0<br />
Bias<br />
voltage<br />
amplifier<br />
0<br />
RF Filters<br />
10 MΩ<br />
10 MΩ<br />
5 MΩ (nom)<br />
Signal ~10 mV<br />
Noise 25 nV/rt(Hz)<br />
Square wave reference<br />
is generated by same<br />
FPGA from same clock<br />
as bias voltage. The<br />
phase between the<br />
reference and bias is<br />
variable<br />
Cold<br />
JFET<br />
amplifier<br />
RF Filters<br />
Additional noise
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