SPIRE Design Description - Research Services
SPIRE Design Description - Research Services
SPIRE Design Description - Research Services
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Draft <strong>SPIRE</strong> <strong>Design</strong> <strong>Description</strong> Document<br />
(iii) Telemetry Data: The telemetry data is the SMEC time counts between two encoder 2 micron<br />
positions and the BSM chop and jiggle positions The telemetry data is transmitted on a fast 16-bit, 1<br />
MHz serial line. The telemetry line is independent of the DSP control and monitoring and is used for<br />
the delivery of data related to the detector signals , with a high level of synchronisation.<br />
Physically, the MCU is composed of a motherboard which acts as the back-plane for the with two MAC<br />
(Multi-axis Controller) boards, the two SMEC boards a the single BSM board. All these boards have a prime<br />
and redundant side. Figure 4-10 shows the schematic block diagram for these boards. The MAC interfaces<br />
via two digital interfaces with the DPU. The first link is a bi-directional 32-bit serial interface for the<br />
transmission of telecommands from the DPU and the retransmission of acknowledge words back to the<br />
DPU. This interface is controlled by a FPGA chip. The commands are then passed to the DSP chip. During<br />
normal operation, the DSP cycles at a frequency between 10 kHz and 3.33 kHz through the following<br />
sequence:<br />
(i) the SMEC digital PID control algorithm is updated;<br />
(ii) the chop stage BSM digital PID control algorithm is updated;<br />
(iii) the jiggle stage BSM digital PID control algorithm is updated;<br />
(iv) the trace table is updated;<br />
(v) any commands from the DPU are uploaded from the FPGA and the acknowledge reply is sent.<br />
DPU<br />
Comm and<br />
Serial Link<br />
Clock<br />
Telemetry<br />
High data<br />
rat e<br />
Serial Link<br />
Command<br />
Serial Link<br />
Interface FPGA<br />
High Rate<br />
Serial Link<br />
Interface<br />
Data<br />
Memory<br />
Command/<br />
Parameters<br />
Parameters<br />
System Status Reply<br />
Clock<br />
Telemetry:<br />
Encoder pulse delta<br />
time , Positions, HK<br />
Data Bus<br />
Command<br />
Interpreter<br />
Timer<br />
time between<br />
pulses<br />
Temp probe signals<br />
Chopper<br />
Position<br />
Trajectory<br />
Profiler<br />
Jiggle<br />
Position<br />
Trajectory<br />
Profiler<br />
SMEC<br />
Trajectory<br />
Profiler<br />
Logics and safety<br />
Quadrature<br />
Counter<br />
66<br />
Chopper<br />
Digital<br />
Controller<br />
Jiggle<br />
Digital<br />
Controller<br />
SMEC<br />
Digital<br />
Controller<br />
21020 DSP<br />
Synchro/<br />
filtering<br />
Telemetry FPGA<br />
DAC<br />
DAC<br />
Mux<br />
ADC<br />
DAC<br />
Digital<br />
I/Os<br />
Sine and<br />
Cosine<br />
0Xing<br />
pulses<br />
MAC Board<br />
Figure 4-10 - Architecture of the MCU.<br />
2x PWR AMP<br />
BSM Board<br />
PWR AMP<br />
Moire fringes<br />
Encoder<br />
Acquisition<br />
Electronics<br />
LVDT/<br />
Home<br />
sensor<br />
Cond.<br />
SMEC<br />
Board<br />
T°C Probes<br />
BSM<br />
Chopper and<br />
Jiggle motor<br />
Magneto-<br />
Resistive<br />
Sensors<br />
BSM<br />
SMECMotor<br />
coil<br />
Moire Fringes<br />
Sensor<br />
Moire fringes<br />
sine signals<br />
@0,120,240°<br />
pre amplifier<br />
The PID algorithm is implemented in software using standard 21020 assembly language without the use of a<br />
specific off-the-shelf real time operating kernel. The assembly language is chosen because Analog Devices<br />
provides directly specific libraries to produce PID, filtering, arctan computation with a high efficiency and<br />
readability.<br />
//<br />
Switches<br />
LVDT<br />
Launch<br />
Latch<br />
SMEC
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