SPIRE Design Description - Research Services
SPIRE Design Description - Research Services
SPIRE Design Description - Research Services
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Draft <strong>SPIRE</strong> <strong>Design</strong> <strong>Description</strong> Document<br />
SYSTEM CONNECTOR 2<br />
BOOT LOGIC<br />
(INSIDE<br />
CONTROL<br />
FPGA)<br />
512Kx48<br />
SRAM<br />
Expanded<br />
PROGRAM MEMORY<br />
PROM 32KB<br />
BOOT MANAGER<br />
MEZZANINE<br />
CONNECTOR A<br />
LATCH<br />
LATCH<br />
LATCH<br />
Data<br />
area<br />
32 bit<br />
words<br />
5.4 Kw<br />
32 KB<br />
512KB<br />
EEPROM<br />
MEZZANINE<br />
Program<br />
area<br />
48 bit<br />
words<br />
INTERVAL<br />
TIMER<br />
512<br />
Kw<br />
2 MB<br />
1 MB<br />
PROM<br />
Kernel<br />
Telemetry<br />
upload SW<br />
512KB<br />
EEPROM<br />
512<br />
Kw<br />
3 MB<br />
MEZZANINE<br />
CONNECTOR B<br />
20 MHz<br />
CLOCK<br />
TSC 21020<br />
JTAG<br />
CONNECTOR<br />
60<br />
IEEE 1355<br />
INTERFACE<br />
SMCS<br />
(TEMIC TSS901)<br />
CONTROL<br />
LOGIC<br />
CONTROL FPGA<br />
DATA MEMORY<br />
Figure 4-4 – CPU board block diagram.<br />
Data<br />
RAM<br />
EEPROM<br />
Inst.<br />
Program<br />
FPGA<br />
State<br />
Machine<br />
Program<br />
RAM<br />
Instr.<br />
Program<br />
From<br />
EEPROM<br />
DPU<br />
TSC 21020<br />
DSP<br />
Figure 4-5 - DPU internal memory<br />
512Kx32<br />
SRAM<br />
Expanded<br />
DUAL<br />
PORT<br />
RAM<br />
16-BIT BUS<br />
INTERFACE<br />
INTERRUPT<br />
MANAGER<br />
WATCHDOG<br />
NOT USED<br />
BOOT<br />
LOGIC<br />
MEZZANINE<br />
INTERFACE<br />
3 S/S<br />
High<br />
Speed<br />
Serial<br />
I/F<br />
3 S/ S<br />
Low<br />
Speed<br />
Serial I/F<br />
Bus<br />
S/C<br />
1355 LINK 1<br />
1355 LINK 2<br />
1355 LINK 3<br />
SYSTEM CONNECTOR 1
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