SPIRE Design Description - Research Services

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Draft SPIRE Design Description Document (iii) Telemetry Data: The telemetry data is the SMEC time counts between two encoder 2 micron positions and the BSM chop and jiggle positions The telemetry data is transmitted on a fast 16-bit, 1 MHz serial line. The telemetry line is independent of the DSP control and monitoring and is used for the delivery of data related to the detector signals , with a high level of synchronisation. Physically, the MCU is composed of a motherboard which acts as the back-plane for the with two MAC (Multi-axis Controller) boards, the two SMEC boards a the single BSM board. All these boards have a prime and redundant side. Figure 4-10 shows the schematic block diagram for these boards. The MAC interfaces via two digital interfaces with the DPU. The first link is a bi-directional 32-bit serial interface for the transmission of telecommands from the DPU and the retransmission of acknowledge words back to the DPU. This interface is controlled by a FPGA chip. The commands are then passed to the DSP chip. During normal operation, the DSP cycles at a frequency between 10 kHz and 3.33 kHz through the following sequence: (i) the SMEC digital PID control algorithm is updated; (ii) the chop stage BSM digital PID control algorithm is updated; (iii) the jiggle stage BSM digital PID control algorithm is updated; (iv) the trace table is updated; (v) any commands from the DPU are uploaded from the FPGA and the acknowledge reply is sent. DPU Comm and Serial Link Clock Telemetry High data rat e Serial Link Command Serial Link Interface FPGA High Rate Serial Link Interface Data Memory Command/ Parameters Parameters System Status Reply Clock Telemetry: Encoder pulse delta time , Positions, HK Data Bus Command Interpreter Timer time between pulses Temp probe signals Chopper Position Trajectory Profiler Jiggle Position Trajectory Profiler SMEC Trajectory Profiler Logics and safety Quadrature Counter 66 Chopper Digital Controller Jiggle Digital Controller SMEC Digital Controller 21020 DSP Synchro/ filtering Telemetry FPGA DAC DAC Mux ADC DAC Digital I/Os Sine and Cosine 0Xing pulses MAC Board Figure 4-10 - Architecture of the MCU. 2x PWR AMP BSM Board PWR AMP Moire fringes Encoder Acquisition Electronics LVDT/ Home sensor Cond. SMEC Board T°C Probes BSM Chopper and Jiggle motor Magneto- Resistive Sensors BSM SMECMotor coil Moire Fringes Sensor Moire fringes sine signals @0,120,240° pre amplifier The PID algorithm is implemented in software using standard 21020 assembly language without the use of a specific off-the-shelf real time operating kernel. The assembly language is chosen because Analog Devices provides directly specific libraries to produce PID, filtering, arctan computation with a high efficiency and readability. // Switches LVDT Launch Latch SMEC
Draft SPIRE Design Description Document The SMEC is typically required follow a saw-tooth position profile as shown in Figure 4-11. The scan nominally starts from 3 mm before the Zero Path Difference (ZPD) position, through to 32 mm. The absolute position of the mirrors vs. time is required in order to be able to obtain a spectrum from the detector signals. This is done in a two step procedure. Position End of Scan ZPD Position Start of Scan 0 Start of Ramp Scientific Scan Flyback Figure 4-11 - SMEC Scan characteristics BSM position sensing: The position of the BSM chop and jiggle stages is monitored via coil inductance. Along with magneto resistive sensing elements. 4.1.2.3 Subsystems Control Unit (SCU) 4.1.3 Detector Control Unit (HSDCU) The Detector Control Unit controls the Detectors of the photometer and the spectrometer, provides the correct detector bias current, conditions the output from the detectors and converts the analogue signals into digital signals. 67 Time
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