SPIRE Design Description - Research Services

Draft SPIRE Design Description Document
transmission up to 350 kbps. This interface is compliant with the MIL-STD-1553B standard, with the DPU
acting as a remote terminal and the spacecraft CDMS acting as the bus controller.
DC/DC Converter: The DC/DC converter is a SMPS running off a spacecraft level clock signal at
131.072 kHz that powers the DPU board. This clock signal synchronises all the SMPSs connected to the
main power bus and avoids the generation of conducted EMI harmonics. The input voltage to the SMPS
provided by the s/c power bus is at 28 V and the nominal output voltage to the CPU board is 5V. The
average power delivered to the DPU is X W.
CPU Board: A schematic representation of the information flow within the DPU is shown in Figure 4-3. On
the top left hand side of the Figure, the DPU “Command-handling” electronics receives and interprets
commands from the CDMS. Upon successful receipt of these commands, a handshake/acknowledge
message is sent back to the bus. The high level commands from the CDMS are processed by the DPU to
provide digital driver commands to the DRCU (which acts as the analogue drive/read out electronics for the
cryogenic part of the instrument) and are in general executed in real time. It is the task of the spacecraft to
determine the sequence and absolute timing of the commands to be passed to SPIRE. These commands are
passed to the DRCU via the “Commanding” block in the lower left hand corner of Figure 4-3. Science
frames and housekeeping data from the instrument are passed to the “Data Collection” block via the highspeed
data interfaces with the DRCU. The housekeeping data (such as instrument temperature, control
currents etc.) are monitored by the “Autonomy” block. In the event of a fault condition in the DRCU or in
the cryogenic section of the instrument, commands are passed to the DRCU to put the instrument into safe
mode. Notification of a fault condition is also passed to the CDMS via the “Packetisation Block” in the top
right corner of Figure 4-3. The CDMS then determines if the instrument should be turned off and unlatches
the LCL for the DRCU and the DPU as necessary. All data passed from the DPU to the CDMS is formatted
according to the ESA Packet Utilisation Standard.
The core microprocessor of the DPU is the TEMIC TSC 21020 which is the Analog Devices 21020 Digital
Signal Processor adapted for space applications by TEMIC. The CPU board is based on this chip (20 MHz
clock), with:
(i) an appropriate timer for time management and synchronisation purposes;
(ii) a watch-dog system that can be hardware disabled through jumper;
(iii) Radiation tolerant memories and components.
Figure 4-4 shows the block diagram for the CPU board. There are three high-speed, unidirectional
synchronous serial 1355 links with a 1 MHz clock between the DRCU and the CPU board. These three links
upload the science data from the DCU. Three serial synchronous buses are used to interface the control
electronics of the focal plane unit subsystems: the bus will be used to transmit commands and receive
responses or to control and receive housekeeping information. The baseline clock speed is 0.2 MHz. Figure
4-5 shows the memory organisation of the CPU and the interfaces between the DPU and the spacecraft and
DRCU with the size of the various types of memories. The CPU directly accesses 1 MB of EEPROM
memory, where the boot sequence software resides. It also accesses 2 MB of SRAM for program data.
58