SPIRE Design Description - Research Services

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. FPGA Sinewave generation Reference 0 0 0 0 Bias voltage amplifier 0 RF Filters 10 MΩ 10 MΩ 5 MΩ (nom) Signal ~10 mV Noise 25 nV/rt(Hz) Square wave reference is generated by same FPGA from same clock as bias voltage. The phase between the reference and bias is variable Cold JFET amplifier RF Filters Additional noise
Draft SPIRE Design Description Document Figure 3-27 - Outline grounding diagram for the SPIRE instrument – this is subject to change and is shown for illustrative purposes only. 53
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SPIRE Design Description - Research Services

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