CME34M Hardware Manual - RTD Embedded Technologies, Inc.

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Jumper Settings and Locations Many cpuModule options are configured by positioning jumpers. Jumpers are labeled on the board as JP followed by a number. Some jumpers have three pins, allowing three settings: • Pins 1 and 2 connected (indicated as “1–2”) • Pins 2 and 3 connected (indicated as “2–3”) • No pins connected 1 2 3 Some jumpers have two pins, allowing two settings: • Pins 1 and 2 connected (indicated as “closed”) • Pins 1 and 2 unconnected (indicated as “open”) 1 2 Figure 9 shows the jumper locations that are used to configure the cpuModule. Table 64 lists the jumpers and their settings. JP5 JP6 90 CME34M cpuModule BDM-610000076 Rev A
Figure 9 CME34M Jumper Locations (top side) Table 64 CME34M Jumpers Jumper Pins Function Default JP5 2 Reserved open JP6 2 Used to disable the Bus Stacking Error detection. See PCIe/104 Type 2 Compatibility on page 42. pins 1–2: Disable Bus Stacking Error detection open: Enable Bus Stacking Error detection (normal operation) open BDM-610000076 Rev A Appendix A: Hardware Reference 91
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CME34M cpuModules User’s Manual B
Page 3 and 4:
CME34M cpuModules www.rtd.com ISO90
Page 5 and 6:
Chapter 1 Introduction Table of Con
Page 7 and 8:
Wake-on-aDIO . . . . . . . . . . .
Page 9 and 10:
Chapter 1 Introduction This manual
Page 11 and 12:
Enhanced Intel SpeedStep (Core 2 Du
Page 13 and 14:
Board Features • Penryn Processor
Page 15 and 16:
- Match Mode Interrupt generates an
Page 17 and 18:
Specifications Physical Characteris
Page 19 and 20:
Table 4 Electrical Characteristics
Page 21 and 22:
Chapter 2 Getting Started For many
Page 23 and 24: Table 5 CME34M Basic Connectors Con
Page 25 and 26: Stack Example The figure below show
Page 27 and 28: Connecting the Utility Cable The mu
Page 29 and 30: Chapter 3 Connecting the cpuModule
Page 31 and 32: Table 6 CME34M Basic Connectors Con
Page 33 and 34: Utility Port Connector (CN5) The ut
Page 35 and 36: Battery Pin 9 of the multi-function
Page 37 and 38: SATA Disk Chip Socket (U6) The SATA
Page 39 and 40: Facing the serial port’s connecto
Page 41 and 42: Dual Serial Port Modes The serial p
Page 43 and 44: Advanced Digital I/O (aDIO) Port (C
Page 45 and 46: Ethernet (10/100/1000Base-T and -TX
Page 47 and 48: Table 26 PCIe/104 Type 2 Bus Signal
Page 49 and 50: PCIe Link Configuration This cpuMod
Page 51 and 52: Chapter 4 Using the cpuModule This
Page 53 and 54: Main Menu Setup Fields The followin
Page 55 and 56: I/O Address Map As with all standar
Page 57 and 58: Non-Standard Serial Port Modes It i
Page 59 and 60: Table 45 DIO-Control I/O Address 9C
Page 61 and 62: Figure 6 aDIO Match Mode Strobe Mod
Page 63 and 64: Table 50 Real Time Clock Registers
Page 65 and 66: Thermal Management The cpuModule ha
Page 67 and 68: • Resume on RTC Alarm: The RTC Al
Page 69 and 70: Reset Status Register The cpuModule
Page 71 and 72: Features and Settings That Can Affe
Page 73: Appendix A Hardware Reference This
Page 77 and 78: Physical Dimensions Figure 10 shows
Page 79 and 80: Appendix B Troubleshooting Many pro
Page 81 and 82: Table 66 Troubleshooting (cont’d)
Page 83 and 84: Appendix C IDAN Dimensions and Pino
Page 85 and 86: External I/O Connections Table 67 P
Page 87 and 88: BDM-610000076 Rev A Appendix C: IDA
Page 89 and 90: Table 72 USB — 9-Pin D Connector
Page 91 and 92: Appendix D Additional Information A
Page 93 and 94: Appendix E Limited Warranty RTD Emb
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