CME34M Hardware Manual - RTD Embedded Technologies, Inc.

PCIe Link Configuration
This cpuModule supports a total of eight PCIe x1 links. The chipset, however, only provides five PCIe x1 links.
Four of the links on CN1 and CN2 are connected directly to the chipset. The other four are connected through
a PCIe packet switch, and share the bandwidth of a single x1 link back to the chipset. The links that are connected
to the PCIe switch do not support wake from S3 (D3cold). Only wake from S1 is supported. Table 27 and Table 28
below shows the configuration of the PCIe x1 links on CN1 and CN2.
Table 27
CN1 Link Configuration
Link BIOS Name Location Connection S3 Wake support PCIe Peer-To-Peer
0 Link 0 Closest to CPU Direct Yes No
1 PCIe Switch Shared No To other Shared
2 PCIe Switch Shared No To other Shared
3 PCIe Switch Farthest from CPU Shared No To other Shared
Table 28
CN2 Link Configuration
Link BIOS Name Location Connection S3 Wake support PCIe Peer-To-Peer
3 Link 3 Closest to CPU Direct Yes No
2 Link 2 Direct Yes No
1 Link 1 Direct Yes No
0 PCIe Switch Farthest from CPU Shared No To other Shared
PCIe Peer-To-Peer
Peer-to-Peer transactions are transactions directly between two PCIe peripheral cards. An example of this is
writing data directly from a data acquisition card to a DSP card, without first writing to the host CPU’s memory.
The PCIe links that are directly connected to the chipset do not support Peer-to-Peer transactions. The shared
PCIe links support peer-to-peer transactions to other shared links. This is reflected in Table 27 above.
Peer-to-peer transactions may also be performed between peripheral cards attached to the x4 links. However,
you cannot do a peer-to-peer transaction between a peripheral on a x4 link and a peripheral on a x1 link.
BDM-610000076 Rev A Chapter 3: Connecting the cpuModule 43