PIC24HJ64 Datasheet

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, AND PIC24HJ128GPX02/X04
REGISTER 7-3: DMAxSTA: DMA CHANNEL x RAM START ADDRESS REGISTER A (1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STA
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STA
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
Note 1:
STA: Primary DMA RAM Start Address bits (source or destination)
A read of this address register returns the current contents of the DMA RAM Address register, not the
contents written to STA. If the channel is enabled (i.e., active), writes to this register may result in
unpredictable behavior of the DMA channel and should be avoided.
REGISTER 7-4: DMAxSTB: DMA CHANNEL x RAM START ADDRESS REGISTER B (1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STB
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STB
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
Note 1:
STB: Secondary DMA RAM Start Address bits (source or destination)
A read of this address register returns the current contents of the DMA RAM Address register, not the contents
written to STB. If the channel is enabled (i.e., active), writes to this register may result in
unpredictable behavior of the DMA channel and should be avoided.
DS70293B-page 106 Preliminary © 2008 Microchip Technology Inc.