PIC24HJ64 Datasheet

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PIC24HJ32GP302/304, <strong>PIC24HJ64</strong>GPX02/X04, AND PIC24HJ128GPX02/X04 The Timer2/3 and Timer4/5 modules can operate in one of the following modes: • Timer mode • Gated Timer mode • Synchronous Counter mode In Timer and Gated Timer modes, the input clock is derived from the internal instruction cycle clock (FCY). In Synchronous Counter mode, the input clock is derived from the external clock input at TxCK pin. The timer modes are determined by the following bits: • TCS (TxCON): Timer Clock Source Control bit • TGATE (TxCON): Timer Gate Control bit Timer control bit settings for different operating modes are given in the Table 12-1. TABLE 12-1: 12.1 16-bit Operation TIMER MODE SETTINGS Mode TCS TGATE Timer 0 0 Gated timer 0 1 Synchronous counter 1 x To configure any of the timers for individual 16-bit operation: 1. Clear the T32 bit corresponding to that timer. 2. Select the timer prescaler ratio using the TCKPS bits. 3. Set the Clock and Gating modes using the TCS and TGATE bits. 4. Load the timer period value into the PRx register. 5. If interrupts are required, set the interrupt enable bit, TxIE. Use the priority bits, TxIP, to set the interrupt priority. 6. Set the TON bit. Note: Only Timer2 and Timer3 can trigger a DMA data transfer. 12.2 32-bit Operation A 32-bit timer module can be formed by combining a Type B and a Type C 16-bit timer module. For 32-bit timer operation, the T32 control bit in the Type B Timer Control (TxCON) register must be set. The Type C timer holds the most significant word (msw) and the Type B timer holds the least significant word (lsw) for 32-bit operation. When configured for 32-bit operation, only the Type B Timer Control (TxCON) register bits are required for setup and control. Type C timer control register bits are ignored (except TSIDL bit). For interrupt control, the combined 32-bit timer uses the interrupt enable, interrupt flag and interrupt priority control bits of the Type C timer. The interrupt control and status bits for the Type B timer are ignored during 32-bit timer operation. The Type B and Type C timers that can be combined to form a 32-bit timer are listed in Table 12-2. TABLE 12-2: TYPE B Timer (lsw) Timer2 Timer4 32-BIT TIMER TYPE C Timer (msw) Timer3 Timer5 A block diagram representation of the 32-bit timer module is shown in Figure 12-3. The 32-timer module can operate in one of the following modes: • Timer mode • Gated Timer mode • Synchronous Counter mode To configure the features of Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 control bit. 2. Select the prescaler ratio for Timer2 or Timer4 using the TCKPS bits. 3. Set the Clock and Gating modes using the corresponding TCS and TGATE bits. 4. Load the timer period value. PR3 or PR5 contains the most significant word of the value, while PR2 or PR4 contains the least significant word. 5. If interrupts are required, set the interrupt enable bits, T3IE or T5IE. Use the priority bits, T3IP or T5IP to set the interrupt priority. While Timer2 or Timer4 controls the timer, the interrupt appears as a Timer3 or Timer5 interrupt. 6. Set the corresponding TON bit. The timer value at any point is stored in the register pair, TMR3:TMR2 or TMR5:TMR4, which always contains the most significant word of the count, while TMR2 or TMR4 contains the least significant word. DS70293B-page 156 Preliminary © 2008 Microchip Technology Inc.
PIC24HJ32GP302/304, <strong>PIC24HJ64</strong>GPX02/X04, AND PIC24HJ128GPX02/X04 FIGURE 12-3: 32-BIT TIMER BLOCK DIAGRAM Gate Sync Falling Edge Detect PRx PRy 1 0 Set TyIF Flag FCY Prescaler (/n) TCKPS 10 00 Comparator lsw msw TMRx TMRy Equal Reset TGATE ADC SOC trigger TxCK Prescaler (/n) Sync x1 TCKPS TGATE TCS TMRyHLD Data Bus Note 1: ADC trigger is available only on TMR3:TMR2 and TMR5:TMR2 32-bit timers 2: Timer x is a Type B Timer (x = 2 and 4) 3: Timer y is a Type C Timer (y = 3 and 5) © 2008 Microchip Technology Inc. Preliminary DS70293B-page 157
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PIC24HJ64 Datasheet

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