PIC24HJ64 Datasheet

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PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, AND PIC24HJ128GPX02/X04 TABLE 6-1: Vector Number INTERRUPT VECTORS (CONTINUED) IVT Address AIVT Address Interrupt Source 47 0x000062 0x000162 Reserved 48 0x000064 0x000164 Reserved 49 0x000066 0x000166 Reserved 50 0x000068 0x000168 Reserved 51 0x00006A 0x00016A Reserved 52 0x00006C 0x00016C Reserved 53 0x00006E 0x00016E PMP – Parallel Master Port 54 0x000070 0x000170 DMA – DMA Channel 4 55 0x000072 0x000172 Reserved 56 0x000074 0x000174 Reserved 57 0x000076 0x000176 Reserved 58 0x000078 0x000178 Reserved 59 0x00007A 0x00017A Reserved 60 0x00007C 0x00017C Reserved 61 0x00007E 0x00017E Reserved 62 0x000080 0x000180 Reserved 63 0x000082 0x000182 Reserved 64 0x000084 0x000184 Reserved 65 0x000086 0x000186 Reserved 66 0x000088 0x000188 Reserved 67 0x00008A 0x00018A Reserved 68 0x00008C 0x00018C Reserved 69 0x00008E 0x00018E DMA5 – DMA Channel 5 70 0x000090 0x000190 RTCC – Real Time Clock 71 0x000092 0x000192 Reserved 72 0x000094 0x000194 Reserved 73 0x000096 0x000196 U1E – UART1 Error 74 0x000098 0x000198 U2E – UART2 Error 75 0x00009A 0x00019A CRC – CRC Generator Interrupt 76 0x00009C 0x00019C DMA6 – DMA Channel 6 77 0x00009E 0x00019E DMA7 – DMA Channel 7 78 0x0000A0 0x0001A0 C1TX – ECAN1 TX Data Request 79 0x0000A2 0x0001A2 Reserved 80 0x0000A4 0x0001A4 Reserved 81 0x0000A6 0x0001A6 Reserved 82 0x0000A8 0x0001A8 Reserved 83 0x0000AA 0x0001AA Reserved 84 0x0000AC 0x0001AC Reserved 85 0x0000AE 0x0001AE Reserved 86 0x0000B0 0x0001B0 Reserved 87 0x0000B2 0x0001B2 Reserved 88-126 0x0000B4-0x0000FE 0x0001B4-0x0001FE Reserved DS70293B-page 64 Preliminary © 2008 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, AND PIC24HJ128GPX02/X04 6.3 Interrupt Control and Status Registers PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, and PIC24HJ128GPX02/X04 devices implement a total of 30 registers for the interrupt controller: • INTCON1 • INTCON2 • IFSx • IECx • IPCx • INTTREG 6.3.1 INTCON1 AND INTCON2 Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit as well as the control and status flags for the processor trap sources. The INTCON2 register controls the external interrupt request signal behavior and the use of the Alternate Interrupt Vector Table. 6.3.2 IFSx The IFS registers maintain all of the interrupt request flags. Each source of interrupt has a status bit, which is set by the respective peripherals or external signal and is cleared via software. 6.3.3 IECx The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. 6.3.4 IPCx The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels. 6.3.5 INTTREG The INTTREG register contains the associated interrupt vector number and the new CPU interrupt priority level, which are latched into vector number (VECNUM) and Interrupt level (ILR) bit fields in the INTTREG register. The new interrupt priority level is the priority of the pending interrupt. The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the same sequence that they are listed in Table 6-1. For example, the INT0 (External Interrupt 0) is shown as having vector number 8 and a natural order priority of 0. Thus, the INT0IF bit is found in IFS0, the INT0IE bit in IEC0, and the INT0IP bits in the first position of IPC0 (IPC0). 6.3.6 STATUS/CONTROL REGISTERS Although they are not specifically part of the interrupt control hardware, two of the CPU Control registers contain bits that control interrupt functionality. • The CPU STATUS register, SR, contains the IPL bits (SR). These bits indicate the current CPU interrupt priority level. The user software can change the current CPU priority level by writing to the IPL bits. • The CORCON register contains the IPL3 bit which, together with IPL, also indicates the current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software. All Interrupt registers are described in Register 6-1 through Register 6-29 in the following pages. © 2008 Microchip Technology Inc. Preliminary DS70293B-page 65
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