PIC24HJ64 Datasheet

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PIC24HJ32GP302/304, <strong>PIC24HJ64</strong>GPX02/X04, AND PIC24HJ128GPX02/X04 FIGURE 3-6: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter (1) 0 Program Counter 0 23 bits EA 1/0 Table Operations (2) 1/0 TBLPAG 8 bits 16 bits 24 bits Select 1 EA 0 Program Space Visibility (1) (Remapping) 0 PSVPAG 8 bits 15 bits 23 bits User/Configuration Space Select Byte Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word aligned. Table read operations are permitted in the configuration memory space. DS70293B-page 44 Preliminary © 2008 Microchip Technology Inc.
PIC24HJ32GP302/304, <strong>PIC24HJ64</strong>GPX02/X04, AND PIC24HJ128GPX02/X04 3.4.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bitwide word address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space that contains the least significant data word. TBLRDH and TBLWTH access the space that contains the upper data byte. Two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. Both function as either byte or word operations. • TBLRDL (Table Read Low): - In Word mode, this instruction maps the lower word of the program space location (P) to a data address (D). - In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘0’. • TBLRDH (Table Read High): - In Word mode, this instruction maps the entire upper word of a program address (P) to a data address. The ‘phantom’ byte (D), is always ‘0’. - In Byte mode, this instruction maps the upper or lower byte of the program word to D of the data address, in the TBLRDL instruction. The data is always ‘0’ when the upper ‘phantom’ byte is selected (Byte Select = 1). In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 4.0 “Flash Program Memory”. For all table operations, the area of program memory space to be accessed is determined by the Table Page register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user application and configuration spaces. When TBLPAG = 0, the table page is located in the user memory space. When TBLPAG = 1, the page is located in configuration space. FIGURE 3-7: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG 02 23 15 0 Program Space 0x000000 23 16 8 0 00000000 00000000 0x020000 0x030000 00000000 00000000 ‘Phantom’ Byte TBLRDH.B (Wn = 0) TBLRDL.B (Wn = 1) TBLRDL.B (Wn = 0) TBLRDL.W 0x800000 The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area. © 2008 Microchip Technology Inc. Preliminary DS70293B-page 45
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PIC24HJ64 Datasheet

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