PIC24HJ64 Datasheet

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PIC24HJ32GP302/304, <strong>PIC24HJ64</strong>GPX02/X04, AND PIC24HJ128GPX02/X04 REGISTER 19-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED) bit 3 SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS = 01 or 1x) When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’ 1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS = 1x); or Samples CH0 and CH1 simultaneously (when CHPS = 01) 0 = Samples multiple channels individually in sequence bit 2 bit 1 bit 0 ASAM: ADC Sample Auto-Start bit 1 = Sampling begins immediately after last conversion. SAMP bit is auto-set. 0 = Sampling begins when SAMP bit is set SAMP: ADC Sample Enable bit 1 = ADC sample/hold amplifiers are sampling 0 = ADC sample/hold amplifiers are holding If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1. If SSRC = 000, software can write ‘0’ to end sampling and start conversion. If SSRC ≠ 000, automatically cleared by hardware to end sampling and start conversion. DONE: ADC Conversion Status bit 1 = ADC conversion cycle is completed. 0 = ADC conversion not started or in progress Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear DONE status (software not allowed to write ‘1’). Clearing this bit does NOT affect any operation in progress. Automatically cleared by hardware at start of a new conversion. DS70293B-page 218 Preliminary © 2008 Microchip Technology Inc.
PIC24HJ32GP302/304, <strong>PIC24HJ64</strong>GPX02/X04, AND PIC24HJ128GPX02/X04 REGISTER 19-2: AD1CON2: ADC1 CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 VCFG — — CSCNA CHPS bit 15 bit 8 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS — SMPI BUFM ALTS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 VCFG: Converter Voltage Reference Configuration bits ADREF+ ADREF- 000 AVDD AVSS 001 External VREF+ AVSS 010 AVDD External VREF- 011 External VREF+ External VREF- 1xx AVDD Avss bit 12-11 Unimplemented: Read as ‘0’ bit 10 CSCNA: Scan Input Selections for CH0+ during Sample A bit 1 = Scan inputs 0 = Do not scan inputs bit 9-8 CHPS: Selects Channels Utilized bits When AD12B = 1, CHPS is: U-0, Unimplemented, Read as ‘0’ 1x = Converts CH0, CH1, CH2 and CH3 01 = Converts CH0 and CH1 00 = Converts CH0 bit 7 BUFS: Buffer Fill Status bit (only valid when BUFM = 1) 1 = ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7 0 = ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF bit 6 Unimplemented: Read as ‘0’ bit 5-2 SMPI: Selects Increment Rate for DMA Addresses bits or number of sample/conversion operations per interrupt. 1111 = Increments the DMA address or generates interrupt after completion of every 16th sample/ conversion operation 1110 = Increments the DMA address or generates interrupt after completion of every 15th sample/ conversion operation • • • 0001 = Increments the DMA address after completion of every 2nd sample/conversion operation 0000 = Increments the DMA address after completion of every sample/conversion operation bit 1 BUFM: Buffer Fill Mode Select bit 1 = Starts buffer filling at address 0x0 on first interrupt and 0x8 on next interrupt 0 = Always starts filling buffer at address 0x0 bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A © 2008 Microchip Technology Inc. Preliminary DS70293B-page 219
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