PIC24HJ64 Datasheet

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PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, AND PIC24HJ128GPX02/X04 TABLE 24-2: WDTPOST FWDT Watchdog Timer Postscaler bits 1111 = 1:32,768 1110 = 1:16,384 • • • 0001 = 1:2 0000 = 1:1 FPWRT FPOR Power-on Reset Timer Value Select bits 111 = PWRT = 128 ms 110 = PWRT = 64 ms 101 = PWRT = 32 ms 100 = PWRT = 16 ms 011 = PWRT = 8 ms 010 = PWRT = 4 ms 001 = PWRT = 2 ms 000 = PWRT = Disabled ALTI2C FPOR Alternate I 2 C pins 1 = I 2 C mapped to SDA1/SCL1 pins 0 = I 2 C mapped to ASDA1/ASCL1 pins BKBUG FICD Background Debug Enable bit 1 = Device will reset in User mode 0 = Device will reset in Debug mode COE FICD Debugger/Emulator Enable bit 1 = Device will reset in Operational mode 0 = Device will reset in Clip-On Emulation mode JTAGEN FICD JTAG Enable bit 1 = JTAG enabled 0 = JTAG disabled ICS FICD ICD Communication Channel Select bits 11 = Communicate on PGC1/EMUC1 and PGD1/EMUD1 10 = Communicate on PGC2/EMUC2 and PGD2/EMUD2 01 = Communicate on PGC3/EMUC3 and PGD3/EMUD3 00 = Reserved, do not use Note 1: PIC24H CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register Description RAM Code Protection is only available on 64K and 128K devices and not implemented on 32K devices. DS70293B-page 256 Preliminary © 2008 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, AND PIC24HJ128GPX02/X04 24.2 On-Chip Voltage Regulator All of the PIC24HJ32GP302/304, PIC24HJ64GPX02/ X04, and PIC24HJ128GPX02/X04 devices power their core digital logic at a nominal 2.5V. This can create a conflict for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, and PIC24HJ128GPX02/X04 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator provides power to the core from the other VDD pins. When the regulator is enabled, a low-ESR (less than 5 Ohms) capacitor (such as tantalum or ceramic) must be connected to the VDDCORE/VCAP pin (Figure 24-1). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor is provided in Table 27-13 located in Section 27.1 “DC Characteristics”. Note: On a POR, it takes approximately 20 μs for the on-chip voltage regulator to generate an output voltage. During this time, designated as TSTARTUP, code execution is disabled. TSTARTUP is applied every time the device resumes operation after any power-down. FIGURE 24-1: It is important for the low-ESR capacitor to be placed as close as possible to the VDDCORE pin. The Brown-out Reset (BOR) module is based on an internal voltage reference circuit that monitors the regulated supply voltage VDDCORE. The main purpose of the BOR module is to generate a device Reset when a brown-out condition occurs. Brown-out conditions are generally caused by glitches on the AC mains (for example, missing portions of the AC cycle waveform due to bad power transmission lines, or voltage sags due to excessive current draw when a large inductive load is turned on). A BOR generates a Reset pulse, which resets the device. The BOR selects the clock source, based on the device Configuration bit values (FNOSC and POSCMD). If an oscillator mode is selected, the BOR activates the Oscillator Start-up Timer (OST). The system clock is held until OST expires. If the PLL is used, the clock is held until the LOCK bit (OSCCON) is ‘1’. Concurrently, the PWRT time-out (TPWRT) is applied before the internal Reset is released. If TPWRT = 0 and a crystal oscillator is being used, then a nominal delay of TFSCM = 100 is applied. The total delay in this case is TFSCM. The BOR Status bit (RCON) is set to indicate that a BOR has occurred. The BOR circuit continues to operate while in Sleep or Idle modes and resets the device should VDD fall below the BOR threshold voltage. 24.3 BOR: Brown-Out Reset CONNECTIONS FOR THE ON-CHIP VOLTAGE 3.3V PIC24H VDD CF VDDCORE/VCAP VSS Note 1: These are typical operating voltages. Refer to Section TABLE 27-13: “Internal Voltage Regulator Specifications” located in Section 27.1 “DC Characteristics” for the full operating ranges of VDD and VDDCORE. 2: It is important for the low-ESR capacitor to be placed as close as possible to the VDDCORE pin. © 2008 Microchip Technology Inc. Preliminary DS70293B-page 257
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PIC24HJ64 Datasheet

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