PIC24HJ64 Datasheet

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PIC24HJ32GP302/304, <strong>PIC24HJ64</strong>GPX02/X04, AND PIC24HJ128GPX02/X04 ECAN Registers Acceptance Filter Enable Register (CiFEN1)............ 199 Acceptance Filter Extended Identifier Register n (CiRXFnEID).................................... 203 Acceptance Filter Mask Extended Identifier Register n (CiRXMnEID)................................... 205 Acceptance Filter Mask Standard Identifier Register n (CiRXMnSID)................................... 205 Acceptance Filter Standard Identifier Register n (CiRXFnSID).................................... 202 Baud Rate Configuration Register 1 (CiCFG1)......... 197 Baud Rate Configuration Register 2 (CiCFG2)......... 198 Control Register 1 (CiCTRL1)................................... 190 Control Register 2 (CiCTRL2)................................... 191 FIFO Control Register (CiFCTRL) ............................193 FIFO Status Register (CiFIFO) ................................. 194 Filter 0-3 Buffer Pointer Register (CiBUFPNT1) ....... 199 Filter 12-15 Buffer Pointer Register (CiBUFPNT4).................................................... 201 Filter 15-8 Mask Selection Register (CiFMSKSEL2) .................................................204 Filter 4-7 Buffer Pointer Register (CiBUFPNT2) ....... 200 Filter 7-0 Mask Selection Register (CiFMSKSEL1) .................................................203 Filter 8-11 Buffer Pointer Register (CiBUFPNT3).................................................... 200 Interrupt Code Register (CiVEC) .............................. 192 Interrupt Enable Register (CiINTE) ........................... 196 Interrupt Flag Register (CiINTF) ............................... 195 Receive Buffer Full Register 1 (CiRXFUL1).............. 206 Receive Buffer Full Register 2 (CiRXFUL2).............. 206 Receive Buffer Overflow Register 2 (CiRXOVF2)...................................................... 207 Receive Overflow Register (CiRXOVF1) .................. 207 ECAN Transmit/Receive Error Count Register (CiEC)......................................................... 197 ECAN TX/RX Buffer m Control Register (CiTRmnCON) .......................................................... 208 Electrical Characteristics...................................................275 AC ............................................................................. 285 Enhanced CAN Module..................................................... 187 Equations Device Operating Frequency .................................... 114 Errata .................................................................................... 8 F Flash Program Memory....................................................... 47 Control Registers ........................................................ 48 Operations .................................................................. 48 Programming Algorithm .............................................. 51 RTSP Operation.......................................................... 48 Table Instructions........................................................ 47 Flexible Configuration ....................................................... 253 I I/O Ports ............................................................................ 125 Parallel I/O (PIO)....................................................... 125 Write/Read Timing .................................................... 126 I 2 C Operating Modes ...................................................... 173 Registers................................................................... 173 In-Circuit Debugger ........................................................... 259 In-Circuit Emulation........................................................... 253 In-Circuit Serial Programming (ICSP) ....................... 253, 259 Input Capture .................................................................... 161 Registers................................................................... 162 Input Change Notification.................................................. 127 Instruction Addressing Modes ............................................ 41 File Register Instructions ............................................ 41 Fundamental Modes Supported ................................. 42 MCU Instructions ........................................................ 41 Move and Accumulator Instructions............................ 42 Other Instructions ....................................................... 42 Instruction Set Overview................................................................... 265 Summary .................................................................. 263 Instruction-Based Power-Saving Modes........................... 123 Idle............................................................................ 124 Sleep ........................................................................ 123 Internal RC Oscillator Use with WDT........................................................... 258 Internet Address ............................................................... 335 Interrupt Control and Status Registers ............................... 65 IECx............................................................................ 65 IFSx ............................................................................ 65 INTCON1.................................................................... 65 INTCON2.................................................................... 65 IPCx............................................................................ 65 Interrupt Setup Procedures................................................. 99 Initialization................................................................. 99 Interrupt Disable ......................................................... 99 Interrupt Service Routine............................................ 99 Trap Service Routine.................................................. 99 Interrupt Vector Table (IVT) ................................................ 61 Interrupts Coincident with Power Save Instructions ......... 124 J JTAG Boundary Scan Interface ........................................ 253 JTAG Interface.................................................................. 259 M Memory Organization ......................................................... 19 Microchip Internet Web Site.............................................. 335 Modes of Operation Disable...................................................................... 189 Initialization............................................................... 189 Listen All Messages.................................................. 189 Listen Only................................................................ 189 Loopback .................................................................. 189 Normal Operation ..................................................... 189 MPLAB ASM30 Assembler, Linker, Librarian ................... 272 MPLAB ICD 2 In-Circuit Debugger ................................... 273 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator.................................................... 273 MPLAB Integrated Development Environment Software ................................................................... 271 MPLAB PM3 Device Programmer .................................... 273 MPLAB REAL ICE In-Circuit Emulator System ................ 273 MPLINK Object Linker/MPLIB Object Librarian ................ 272 Multi-Bit Data Shifter........................................................... 18 N NVM Module Register Map .............................................................. 40 O Open-Drain Configuration................................................. 126 Output Compare ............................................................... 163 DS70293B-page 330 Preliminary © 2008 Microchip Technology Inc.
PIC24HJ32GP302/304, <strong>PIC24HJ64</strong>GPX02/X04, AND PIC24HJ128GPX02/X04 P Packaging ......................................................................... 317 Details ....................................................................... 318 Marking ..................................................................... 317 Peripheral Module Disable (PMD) .................................... 124 PICSTART Plus Development Programmer ..................... 274 Pinout I/O Descriptions (table) ............................................ 11 PMD Module Register Map............................................................... 40 PORTA Register Map......................................................... 38, 39 PORTB Register Map............................................................... 39 Power-on Reset (POR) ....................................................... 58 Power-Saving Features .................................................... 123 Clock Frequency and Switching................................ 123 Program Address Space..................................................... 19 Construction................................................................ 43 Data Access from Program Memory Using Program Space Visibility........................... 46 Data Access from Program Memory Using Table Instructions ............................................... 45 Data Access from, Address Generation...................... 44 Memory Map ............................................................... 19 Table Read Instructions TBLRDH ............................................................. 45 TBLRDL .............................................................. 45 Visibility Operation ...................................................... 46 Program Memory Interrupt Vector ........................................................... 20 Organization................................................................ 20 Reset Vector ............................................................... 20 R Reader Response ............................................................. 336 Register Map CRC ............................................................................ 38 Dual Comparator......................................................... 38 Parallel Master/Slave Port .......................................... 37 Real-Time Clock and Calendar................................... 38 Registers AD1CHS0 (ADC1 Input Channel 0 Select ................ 223 AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)............................................................ 222 AD1CON1 (ADC1 Control 1) .................................... 217 AD1CON2 (ADC1 Control 2) .................................... 219 AD1CON3 (ADC1 Control 3) .................................... 220 AD1CON4 (ADC1 Control 4) .................................... 221 AD1CSSL (ADC1 Input Scan Select Low)................ 224 AD1PCFGL (ADC1 Port Configuration Low) ............ 224 CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer)........... 199 CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer)........... 200 CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer)......... 200 CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer) ............................................................. 201 CiCFG1 (ECAN Baud Rate Configuration 1) ............ 197 CiCFG2 (ECAN Baud Rate Configuration 2) ............ 198 CiCTRL1 (ECAN Control 1) ...................................... 190 CiCTRL2 (ECAN Control 2) ...................................... 191 CiEC (ECAN Transmit/Receive Error Count)............ 197 CiFCTRL (ECAN FIFO Control)................................ 193 CiFEN1 (ECAN Acceptance Filter Enable) ............... 199 CiFIFO (ECAN FIFO Status)..................................... 194 CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection).................................................. 203, 204 CiINTE (ECAN Interrupt Enable) .............................. 196 CiINTF (ECAN Interrupt Flag) .................................. 195 CiRXFnEID (ECAN Acceptance Filter n Extended Identifier) .......................................... 203 CiRXFnSID (ECAN Acceptance Filter n Standard Identifier)........................................... 202 CiRXFUL1 (ECAN Receive Buffer Full 1)................. 206 CiRXFUL2 (ECAN Receive Buffer Full 2)................. 206 CiRXMnEID (ECAN Acceptance Filter Mask n Extended Identifier).............................. 205 CiRXMnSID (ECAN Acceptance Filter Mask n Standard Identifier) .............................. 205 CiRXOVF1 (ECAN Receive Buffer Overflow 1)........ 207 CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 207 CiTRBnSID (ECAN Buffer n Standard Identifier) .......................................... 209, 210, 212 CiTRmnCON (ECAN TX/RX Buffer m Control) .............................................. 208 CiVEC (ECAN Interrupt Code) ................................. 192 CLKDIV (Clock Divisor) ............................................ 119 CORCON (Core Control)...................................... 17, 67 DMACS0 (DMA Controller Status 0) ........................ 108 DMACS1 (DMA Controller Status 1) ........................ 110 DMAxCNT (DMA Channel x Transfer Count)........... 107 DMAxCON (DMA Channel x Control)....................... 104 DMAxPAD (DMA Channel x Peripheral Address) ........................................................... 107 DMAxREQ (DMA Channel x IRQ Select) ................. 105 DMAxSTA (DMA Channel x RAM Start Address A) ............................................... 106 DMAxSTB (DMA Channel x RAM Start Address B) ............................................... 106 DSADR (Most Recent DMA RAM Address) ............. 111 I2CxCON (I2Cx Control)........................................... 175 I2CxMSK (I2Cx Slave Mode Address Mask)............ 179 I2CxSTAT (I2Cx Status) ........................................... 177 IFS0 (Interrupt Flag Status 0) ............................... 70, 77 IFS1 (Interrupt Flag Status 1) ............................... 72, 79 IFS2 (Interrupt Flag Status 2) ............................... 74, 81 IFS3 (Interrupt Flag Status 3) ............................... 75, 82 IFS4 (Interrupt Flag Status 4) ............................... 76, 83 INTCON1 (Interrupt Control 1) ................................... 68 INTCON2 (Interrupt Control 2) ................................... 69 INTTREG Interrupt Control and Status Register................................................... 98 IPC0 (Interrupt Priority Control 0) ............................... 84 IPC1 (Interrupt Priority Control 1) ............................... 85 IPC11 (Interrupt Priority Control 11) ........................... 94 IPC15 (Interrupt Priority Control 15) ........................... 95 IPC16 (Interrupt Priority Control 16) ........................... 96 IPC17 (Interrupt Priority Control 17) ........................... 97 IPC2 (Interrupt Priority Control 2) ............................... 86 IPC3 (Interrupt Priority Control 3) ............................... 87 IPC4 (Interrupt Priority Control 4) ............................... 88 IPC5 (Interrupt Priority Control 5) ............................... 89 IPC6 (Interrupt Priority Control 6) ............................... 90 IPC7 (Interrupt Priority Control 7) ............................... 91 IPC8 (Interrupt Priority Control 8) ............................... 92 IPC9 (Interrupt Priority Control 9) ............................... 93 NVMCON (Flash Memory Control)............................. 49 NVMKEY (Nonvolatile Memory Key) .......................... 50 OCxCON (Output Compare x Control) ..................... 165 OSCCON (Oscillator Control)................................... 117 OSCTUN (FRC Oscillator Tuning)............................ 121 PLLFBD (PLL Feedback Divisor) ............................. 120 RCON (Reset Control)................................................ 54 SPIxCON1 (SPIx Control 1) ..................................... 169 SPIxCON2 (SPIx Control 2) ..................................... 171 © 2008 Microchip Technology Inc. Preliminary DS70293B-page 331
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PIC24HJ64 Datasheet

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